QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 671 POWER-OVER-ETHERNET INTERFACE CONTROLLER LTC4257CS8-1 DESCRIPTION Demonstration circuit 671 provides a complete IEEE The LTC4257-1 simplifies Powered Device (PD) de- 802.3af interface and isolated 3.3V power supply so- sign by incorporating the 25k signature resistor, lution for use in PD Phone applications. The classification current source, inrush current limit, un- LTC 4257 performs signature, classification, and der-voltage lockout, thermal current limit, and power power interface functions to switch power to a 48V to good signaling, all in a single 8-pin package. The 3.3V isolated Flyback converter featuring the LT1737. LT1737 provides efficient conversion from 48V to 3.3V. Design files for this circuit board are available. Call the LTC factory. LTC is a trademark of Linear Technology Corporation Table 1. Typical Performance Summary PARAMETER CONDITION VALUE Maximum Turn On Voltage PD Power Up 42V Minimum Turn Off Voltage PD Power Down 30V Minimum Operating Input Voltage In from PSE 36V Maximum Operating Input Voltage In from PSE 57V Maximum Input Power In from PSE 12.95W Maximum Input Current In from PSE, Vin = 37V 350mA In from PSE, Vin = 57V 230mA Maximum Output Current Vin = 37V 3.3A Output Voltage V 3.3V 2% OUT QUICK START PROCEDURE Demonstration circuit 671 connects to a PSE for 2. Set JP2 to Enable to enable the LTC4257-1. quick evaluation of the LTC4257-1 with the LT1737. 3. Connect a 0 to 3.3A load and meters to the Refer to Figure 1 for proper measurement equip- VOUT pins. ment setup and follow the procedure below: 4. Connect with an Ethernet cable from an 1. Set JP1 to a selected PD Class of 0 through IEEE802.3af compliant PSE to J2. 4. 1QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 671 POWER-OVER-ETHERNET INTERFACE CONTROLLER OPERATION Demonstration circuit 671 interfaces with a cus- Power Signature (MPS). The LTC4257-1 holds its tomers Power-Over-Ethernet test setup per Figure 1. 25k signature resistance to satisfy the AC MPS. The front end of the demo circuit implements re- However, the PD must hold the DC MPS by drawing quired Ethernet transformer coupling via transformer at least 10mA or the PSE may disconnect power. T2. Common-mode termination (R1, R2, R30, R31) This demonstration circuit draws more than 10mA is provided along with a 2KV capacitor (C2). The when on. Therefore an IEEE compliant PSE would demo circuit is setup to allow data to pass in and maintain power after detection due to the DC load back out of the demo circuit while the DC671 per- current. forms IEEE 802.3af interface functions. The Power JP2 enables or disables the LTC4257-1 functions and Sourcing Equipment (PSE) is connected to J2 and the 25k signature resistance. PHY is optionally connected to J1. The synchronous Flyback converter operates at a Schottky diodes used in a diode bridge configuration nominal switching frequency of 200kHz, controlled by on the input signal lines and the spare lines on the the LT1737. Galvanic isolation is met with transform- front end allows the PD to meet the auto-polarity re- ers T1 and T3. C23 is used as a local bypass to re- quirements of IEEE802.3af. Because of the smaller duce common-mode currents. voltage drop than standard diodes, they also provide The primary side power path is comprised of T1, Q3, higher efficiency than typical diode bridges. R15, and C8. These components should be as close The PD is required to have 0.1uF of capacitance dur- as possible when laying out the printed circuit board. ing detection and this is provided by C11. It is also Power is transferred during the off time of Q3. Q6 is required to have at least 5uF of capacitance after the the secondary synchronous rectifier. C4 to C6 form in-rush circuit, provided by capacitors C7, C8 and the secondary output filter. L1, C7, and C8 form the C15. primary input filter. An auxiliary winding on T1 per- This demo circuit allows detection and power classifi- forms two functions: it provides output feedback in- cation of the PD per the IEEE 802.3af specification. formation and supplies bias voltage to the LT1737. A During the detection process of a PD, the LTC4257-1 driver, comprised of Q7 and Q8, synchronizes with displays the proper 25k signature resistor. A cur- the LT1737 via T3 to provide gate drive to the secon- rent source is implemented within the LTC4257-1 and dary switching MOSFET. The output voltage can be is programmed by the selection of a single external modified with the selection of R13 and R23. resistor. The class 0-4 current sources can easily be The maximum input power of a PD is 12.95W. set in this demo circuit with the placement of a single IEEE802.3af specifies that at 37V, the steady-state jumper on JP1. input current to a PD is limited to a maximum of After detection and classification, the PD is powered 350mA and the designer must insure their PD does up. When the voltage exceeds the LTC4257-1 turn-on not draw more than this amount while in the highest UVLO, power is switched over to the switching regu- power mode. To avoid an over-current situation (350 lator. The Power Good output pulls active low to sig- to 400mA for over 50ms, or above 400mA) during nal to the LT1737 to begin operation. This allows for startup, this demo circuit also implements a soft-start the capacitors to be charged first before the regulator function. The output voltage of LTC4257-1 ramps up starts to avoid exceeding the limited inrush current. to the final value over several milliseconds while the input current stays below the 350mA limit. For the PD to remain powered on, it must present to the PSE both AC and DC components of the Maintain 2