QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 794 TRIPLE HIGH SPEED VIDEO BUFFER LT6554 DESCRIPTION Demonstration Circuit 794 is a Triple High Speed cates the performance that is achieved with this Video Buffer featuring the LT6554. This circuit is de- evaluation board. signed to demonstrate DC-coupled performance in Design files for this circuit board are available. Call either split- or single-supply operation. Table 1 indi- the LTC factory. Table 1. Performance Summary (T = 25C) A PARAMETER CONDITION VALUE Split supply operation, Min/Max 2.3V/6V Supply Voltage Single supply operation, Min/Max +4.5/+12V Input Impedance, INR, ING, INB 75W, dc-coupled to ground Output Impedance, OUTR, OUTG, OUTB 75W, dc-coupled CAL trace Impedance 75W nominal Outputs terminated into 75W -6dB nominal Gain Outputs terminated into High impedance 0dB nominal Bandwidth 3dB, outputs terminated in 75W, -13dBm input 450MHz typical Worst-case All Hostile, 10MHz 75dB typical Crosstalk Worst-case All Hostile, 100MHz 50dB typical 3.3V Split Supply, No Output Clipping, Hi-Z loading 2.0V Input Signal Voltage Range 5.0V Split Supply, No Output Clipping, Hi-Z loading 3.7V +9.0V Single Supply, No Output Clipping, Hi-Z loading +1.3 to +7.7V Logic Low Voltage (Amplifiers ON), DGND = 0V 0.8V On/Off Control Input Logic High Voltage (Amplifiers OFF), DGND = 0V 2.0V (5.5V max) OPERATING PRINCIPLES DC794 provides three identical channels of wideband to the local analog ground (AGND) for example, signal buffering suitable for driving HDTV or high- when the logic source is floating or none is used dur- resolution RGB video multiplexers or digitizers. Each ing the evaluation. DGND may be left uncommitted buffer section of the LT6554 provides a fixed gain of with JP2 in the FLOAT position. 1 to a destination load. Each input is terminated to Another jumper, JP1, allows the LT6554 to be forced analog ground to properly load the input signal ca- to an ENABLE condition. If JP1 is left in the EXTernal bles. position, then enabling the LT6554 is accomplished To minimize ingress of external digital ground noise, by pulling down the EN connection to a level near that the DGND logic reference input is decoupled from of DGND via connection to E1 or J1. A pull-up resis- analog ground within the LT6554. DC794 includes a tor internal to the LT6554 will provide a default shut- jumper, JP2, which allows the DGND to be strapped down mode of operation if the control input is left 1 QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 794 TRIPLE HIGH SPEED VIDEO BUFFER open-circuit. NOTE: DO NOT open-circuit EN if V+ is to be eliminated from the transmission measure- more than 5.5V above DGND refer to LT6554 data- ments. sheet for application details in this situation. JP3 is provided as a convenience to eliminate having A CAL trace is also provided on DC794 to provide a to externally short V to GND in the case of SINGLE means of precision calibration for a Network Analyzer supply operation. Leave JP3 in the DUAL position (use the CAL connections when performing the when using split supplies. THRU transmission calibration). The CAL trace has Figure 4 shows the material list of the components the same electrical performance and delay as the used by DC794, and Figure 5 shows the electrical in- transmission lines of the three signal channels, terconnection. thereby allowing circuit board and connector effects QUICK START PROCEDURE Demonstration Circuit 794 is easy to set up to evalu- equal-length 75W cabling amongst the three video ate the performance of the LT6554. Refer to Figure 1 channels. Figure 3 shows a typical pulse response. for proper measurement equipment setup and follow 6. If using a Network Analyzer, perform the THRU the procedure below: transmission calibration with all cabling, adapters, NOTE: Due to the Ultra High Frequencies (UHF) in- impedance converters, etc. in place, and using the volved, RF measurement practices are required to DC794 CAL trace as the reference 0dB path. accurately evaluate the performance of the LT6554. 7. Connect a Network Analyzer (if used) to the appro- 1. Place jumpers in the following positions: priate channels to measure frequency response and crosstalk as desired. Figure 2 shows a typical JP1 ENABLE transmission plot for 1k loading. Use of 75W load- JP2 AGND ing with the DC794 as shipped will reduce the -3dB response to about 450MHz (and show a passband JP3 DUAL loss of -6dB). If the analyzer has only a low- 2. Prior to connecting the power supply, preset the impedance input, then the R =1kW condition can L output voltages to 5V, or to the desired level, if be simulated by installing 953W resistors in R1, different. R2, and R3 and providing a 26.05dB correction to the 50W analyzer reading (or 22.74dB for a 75W 3. With power off, connect the power supplies to V+, instrument). V, and GND using banana-plug cables. 8. To evaluate the shutdown mode, disconnect or re- 4. Energize the power supply. locate the JP1 jumper to the EXT position (with no 5. For video-signal evaluation, connect a component- connections made at EN, or if present, a logic high video signal source to the inputs and a high input provided). impedance video analyzer to the outputs, using 2