DEMO MANUAL DC981A/DC981B LTC4263 Main Board, Single Port Autonomous PSE/Daughter Card PSE DESCRIPTION Demonstration circuits 981A and 981B feature the PSE implementation, needing only a single 48V supply LTC 4263 in single port Power over Ethernet (PoE) power and a small number of passive support components. sourcing equipment (PSE) midspan and endpoint solu- Other options shown on the DC981A include legacy PD tions. The LTC4263 is an autonomous single-channel PSE detection enable, midspan backoff timer enable, power controller for use in IEEE802.3af compliant PoE systems. class enforce mode, and power management enable. An It includes an onboard planar power MOSFET, internal LED for each port is driven by the respective LTC4263 inrush, current limit, and short-circuit control, powered to indicate the state of the port. The DC981A is Ethernet device (PD) detection and classification circuitry, and Alliance certified. selectable AC or DC disconnect sensing. Onboard control Design files for this circuit board are available. algorithms provide complete PSE control operation without All registered trademarks and trademarks are the property of their respective owners. the need of a microcontroller. The LTC4263 simplifies PERFORMANCE SUMMARY Table 1. Typical DC981, Specifications are at T = 25C A PARAMETER CONDITION VALUE Supply Voltage Voltage for IEEE802.3af Compliance at Port Output 46V to 57V Midspan Mode Detection Backoff Midspan Enabled, Failed Detection 3.2s Detection Range Valid IEEE802.3af PD Detection 17k to 29.7k Set Maximum Allocated Power Power Management Enabled, RPM = 12.4k 17W Ethernet Powered Pairs Pinout Endpoint PSE, Alternative A (MDI) 1/2(+), 3/6() Midspan PSE, Alternative B 4/5(+), 7/8 () QUICK START PROCEDURE Demonstration circuits 981A and 981B are easy to set 3. Apply 48V across VDD48 and VSS. up to evaluate the performance of the LTC4263. Refer to 4. Connect a scope probe at VOUT MD and VOUT EP Figure 1 for proper measurement equipment setup and both referenced to positive rail VDD48. follow the procedure below. 5. Connect a valid PD to either midspan PSE or 1. Place jumpers in the following positions: endpoint PSE. JP1 EN 6. Connect a second PD to the open port. JP2 EN JP3 DIS JP4 AC JP5 AC JP6 EN 2. Insert daughter card (DC981B) to main board (DC981A) at polarized connector J3. Rev A 1DEMO MANUAL DC981A/DC981B OPERATING PRINCIPLES www.analog.com Figure 1. Basic DC981A/DC981B Equipment Setup Rev A 2