QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 998A NEGATIVE HOT SWAP CONTROLLER WITH ADC AND I2C MONITORING LTC4261CGN DESCRIPTION Demonstration Circuit 998A showcases the The -48V input, RTN and -48V output are separated from each other by at least 55 mils spacing. Input and LTC 4261 negative Hot Swap controller with ADC output connections are made by 93 mil turrets which and I2C monitoring in a 200W, 36 to 72V application. if removed, accommodate insertion of up to 12 gauge Included on board is isolation for power good control wires for in-situ testing. pins and the single wire interface output. LEDs indi- cate the presence of -48V input and output, as well as Design files for this circuit board are available. Call the state of numerous I/O pins. Jumpers allow maxi- the LTC factory. mum flexibility in examining the many features of the LTC is a registered trademark of Linear Technology Corporation LTC4261. Table 1. Performance Summary (T = 25C) A SYMBOL PARAMETER CONDITION MIN TYP MAX UNITS UV ON 42.5 43 43.5 V -48V UV OFF 37.5 38.5 39.5 V INPUT OV OFF 77 V OV ON 68 V I , CB CIRCUIT BREAKER TRIP CURRENT 5.5 6.25 7 A OUT OPERATING PRINCIPLES The top of the board contains the components ger- Clamps on the input and output prevent avalanche in mane to a typical application, along with indicating the MOSFET. LEDs, connection turrets, and jumpers to configure various features and I/O pins. The 93-mil turrets are Changing Current Levels not swaged and may be removed for attachment of up to 12 gauge wire. The board can deliver 200W The board may be modified for other current levels. over the full operating range. The LTC4261 current sense voltage range is 45 to 55mV, and space is provided for up to three, 1W The bottom of the board contains components not sense resistors corresponding to a current of about associated with the LTC4261 typical application, such 50A. Copper loss is about 1.2 milliohms, equivalent as optional I2C bus monitoring, scaling resistors for to about 2 squares of 1-ounce copper this excludes the A/D inputs, and protection resistors to make the MOSFET and sense resistor losses. demo circuit more resistant to careless mistakes in a bench-testing environment. Two important compo- A clear line of demarcation separates RTN, -48V nents are located on the bottom of the board bypass INPUT, and -48V OUTPUT, with a spacing of at least capacitors for INTVCC and VIN are placed there to 55 mils to any adjacent trace. Since the LTC4261 achieve short, direct path. uses a shunt regulated supply, there is no high volt- age present across any package pins. DRAIN con- 1 QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 998A NEGATIVE HOT SWAP CONTROLLER WITH ADC AND I2C MONITORING nects to the output through RD, which serves to J1, I2C INTERFACE. See separate section covering block the high voltage sometimes present there. this topic. RAMP reaches the output through capacitor, CR. Similarly, RIN1-3 stand off high voltage at RTN. JP7, SDA. The LTC4261 has a split SDA function, appearing as the SDAI (input) and SDAO (output) Although PGIO and PG are designed to withstand pins. These two pins facilitate optical isolation. JP7 is 100V, they lack 55 mil spacing to adjacent package initially jumpered in the COM (common) position, pins. Nevertheless, care has been taken to situate which shorts SDAI and SDAO together and allows the these pins at one corner of the package, and EN has board to operate with DC590A. If JP4 is moved to the been placed as a guard to minimize leakage issues SPLIT position, these pins are separated. into surrounding circuitry. In addition if flashover oc- curs, PGIO and PG are used with series resistors (in JP3, INTERFACE. Selects between I2C and SINGLE this case 24 kohms) which limit the flow of current WIRE interface modes. This jumper moves SDAO be- and readily stand off the operating voltage and any tween JP3 (I2C) and the HCPL-0300 optical isolator. transients. JP2, EN . Connects EN HIGH (INTVCC, disable), Jumpers LOW (VEE, enable), or EXT (adjacent turret). Default is low to enable the LTC4261 on power up. DC998A contains 11 jumpers, and a 14-pin connector for I2C interface (discussed later in the I2C Interface JP5, UV/OV. Connects top of UV and OV dividers to section). The jumpers either configure a pin or pro- RTN or adjacent SHORT PIN turret. Default is RTN. vide a means for bringing the associated pin out to a turret for external connections. A description of each JP1, PGIO. PGIO pin has three possible functions it jumper follows. The purpose of this section is not to can be an I2C programmable open collector output, a replicate the data sheet. For further details refer to logic input read by I2C or (the default) a power good that document. output. JP1 gives the choice of connecting PGIO to an opto isolator (OPTO, default jumper position), or JP10 and JP4, I2C Address ADR0 and ADR1. These to the PGIO turret (EXT). jumpers program the I2C address for the board. The address pins ADR0 and ADR1 are 3-state inputs they JP6, PGI . The LTC4261 monitors a down-stream can be LOW (VEE), OPEN, or HIGH (INTVCC). The DC-DC converter by watching for PGI to go low default stuffing is low-low, which corresponds to a within a timer interval during power up. If PGI does device write address of 0010000 (20h). An address of not go low, the LTC4261 shuts down. JP6 offers con- ADR0=low and ADR1=high puts the LTC4261 in Sin- nections to an opto isolator (OPTO) or connects PGI gle-Wire Broadcast Mode, and free-running serial to VEE (BYPASS). BYPASS is the default jumper posi- data appears atSingle Wire Interfac (connect a tion, which ignores the state of the opto isolator. separate, 5V supply to power opto U2). JP9, ADIN. Moves ADIN between the ADIN turret JP8, ON. Selects between forcing the ON pin HIGH (EXT) and a divider to the -48V output (default) which (INTVCC), LOW (VEE), or EXT, which passes the pin measures VDS. through to the adjacent ON turret. The default is ON=high, which allows the part to turn on independ- ent of I2C control. 2