DS1100L 3.3V 5-Tap Economy Timing Element (Delay Line) GENERAL DESCRIPTION FEATURES The DS1100L is a 3.3V version of the DS1100. It All-Silicon Timing Circuit is characterized for operation over the range 3.0V Five Taps Equally Spaced to 3.6V. The DS1100L series delay lines have Delays are Stable and Precise five equally spaced taps providing delays from Both Leading- and Trailing-Edge Accuracy 4ns to 500ns. These devices are offered in 3.3V Version of the DS1100 surface-mount packages to save PCB area. Low Low-Power CMOS cost and superior reliability over hybrid TTL-/CMOS-Compatible technology is achieved by the combination of a Vapor-Phase and IR Solderable 100% silicon delay line and industry-standard Custom Delays Available MAX and SO packaging. The DS1100L 5-tap Fast-Turn Prototypes silicon delay line reproduces the input-logic state Delays Specified Over Both Commercial and at the output after a fixed delay as specified by Industrial Temperature Ranges the extension of the part number after the dash. The DS1100L is designed to reproduce both PIN ASSIGNMENT leading and trailing edges with equal precision. IN 1 8 V CC Each tap is capable of driving up to 10 74LS loads. TAP 2 2 7 TAP 1 DS1100L Maxim Integrated can customize standard products to meet special needs. TAP 4 3 6 TAP 3 GND 4 5 TAP 5 MAX is a registered trademark of Maxim Integrated Products, Inc. DS1100LZ SO (150mils) DS1100LU MAX PIN DESCRIPTION TAP 1 to TAP 5 - TAP Output Number V - +3.3V CC GND - Ground IN - Input 19-5736 Rev 7/15 1 of 7 DS1100L ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground ........................................... -0.5V to +6.0V Short-Circuit Output Current ............................................................................ 50mA for 1s Continuous Power Dissipation (T = +70 C) A SO (derate 5.9mW/C above +70 C) ................................................................ 470.6mW MAX (derate 4.5mW/C above +70 C .............................................................. 362mW Operating Temperature Range .................................................................... -40C to +85C Storage Temperature Range ...................................................................... -55C to +125C Lead Temperature (soldering, 10s)........................................................................... +300 C Soldering Temperature (reflow) Lead(Pb)-free ........................................................................................................ +260 C Containing lead(Pb) ............................................................................................... +240 C This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. DC ELECTRICAL CHARACTERISTICS (V = 3.0V to 3.6V T = -40C to +85C, unless otherwise noted.) CC A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES Supply Voltage V 3.0 3.3 3.6 V 5 CC High-Level V + CC V 2.0 V 5 IH Input Voltage 0.3 Low-Level V -0.3 0.8 V 5 IL Input Voltage Input-Leakage I -1.0 +1.0 A 0.0V V V I I CC Current Active Current I V = Max Freq. = 1MHz 10 mA 6, 8 CC CC High-Level I V = Min. V = 2.3 -1 mA OH CC OH Output Current Low-Level I V = Min. V = 0.5 8 mA OL CC OL Output Current AC ELECTRICAL CHARACTERISTICS (V = 3.0V to 3.6V T = -40C to +85C, unless otherwise noted.) CC A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES 20% of Input t Tap 5 ns 9 WI Pulse Width t PLH 1, 3, 4, +25C 3.3V -2 Table 1 +2 ns 7, 10 Input-to-Tap t 1, 2, 3, PLH, Delay Tolerance 0C to +70C -3 Table 1 +3 ns t 4, 7, 10 PHL (Delays 40ns) 1, 2, 3, -40C to +85C -4 Table 1 +4 ns 4, 7, 10 1, 3, 4, +25C 3.3V -5 Table 1 +5 % 7, 10 Input-to-Tap t 1, 2, 3, PLH, Delay Tolerance 0C to +70C -8 Table 1 +8 % t 4, 7, 10 PHL (Delays > 40ns) 1, 2, 3, -40C to +85C -13 Table 1 +13 % 4, 7, 10 Output Rise or Fall t , t 2.0 2.5 ns OF OR Time Power-Up Time t 200 s PU Input Period Period 2(t ) ns 9 WI 2 of 7