19-6294 Rev 6/12 DS1210 Nonvolatile Controller Chip FEATURES PIN ASSIGNMENT Converts CMOS RAMs into Nonvolatile VCCO 1 8 VCCI Memories Unconditionally Write Protects when V is VBAT1 2 7 VBAT2 CC Out-of-Tolerance TOL 3 6 CEO Automatically Switches to Battery when GND 4 5 CE Power-Fail Occurs DS1210 8-pin PDIP (300 mils) Space-Saving 8-Pin PDIP or 16-Pin SO Packages NC 1 NC 16 Consumes <100nA of Battery Current VCCO VCCI 2 15 Tests Battery Condition on Power up NC NC 3 14 VBAT1 VBAT2 Provides for Redundant Batteries 4 13 NC NC 5 12 Optional 5% or 10% Power-Fail Detection TOL CEO 6 11 Low Forward Voltage Drop on the V CC NC NC 7 10 Switch GND CE 8 9 Optional Industrial (N) Temperature Range of DS1210S 16-pin SO (300 mils) -40C to +85C PIN DESCRIPTION V - RAM Supply CCO V - + Battery 1 BAT1 TOL - Power Supply Tolerance GND - Ground CE - Chip Enable Input CEO - Chip Enable Output V - + Battery 2 BAT2 V - + Supply CCI NC - No Connect DESCRIPTION The DS1210 Nonvolatile Controller Chip is a CMOS circuit which solves the application problem of converting CMOS RAM into nonvolatile memory. Incoming power is monitored for an out-of-tolerance condition. When such a condition is detected, chip enable is inhibited to accomplish write protection and the battery is switched on to supply the RAM with uninterrupted power. Special circuitry uses a low- leakage CMOS process which affords precise voltage detection at extremely low battery consumption. The 8-pin DIP package keeps PC board real estate requirements to a minimum. By combining the DS1210 Nonvolatile Controller Chip with a CMOS memory and batteries, nonvolatile RAM operation can be achieved. 1 of 8 DS1210 OPERATION The DS1210 nonvolatile controller performs five circuit functions required to battery back up a RAM. First, a switch is provided to direct power from the battery or the incoming supply (V ) depending on CCI which is greater. This switch has a voltage drop of less than 0.3V. The second function which the nonvolatile controller provides is power-fail detection. The DS1210 constantly monitors the incoming supply. When the supply goes out of tolerance, a precision comparator detects power-fail and inhibits chip enable ( CEO ). The third function of write protection is accomplished by holding the CEO output signal to within 0.2 volts of the V or battery supply. If CE input is low at the time power-fail detection occurs, the CEO CCI output is kept in its present state until CE is returned high. The delay of write protection until the current memory cycle is completed prevents the corruption of data. Power-fail detection occurs in the range of 4.75 volts to 4.5 volts with the tolerance (TOL) pin grounded. If TOL in connected to V , then power- CCO fail detection occurs in the range of 4.5 volts to 4.25 volts. During nominal supply conditions CEO will follow CE with a maximum propagation delay of 20ns. The fourth function the DS1210 performs is a battery status warning so that potential data loss is avoided. Each time that the circuit is powered up the battery voltage is checked with a precision comparator. If the battery voltage is less than 2.0 volts, the second memory cycle is inhibited. Battery status can, therefore, be determined by performing a read cycle after power-up to any location in memory, verifying that memory location content. A subsequent write cycle can then be executed to the same memory location altering the data. If the next read cycle fails to verify the written data, then the batteries are less than 2.0V and data is in danger of being corrupted. The fifth function of the nonvolatile controller provides for battery redundancy. In many applications, data integrity is paramount. In these applications it is often desirable to use two batteries to ensure reliability. The DS1210 controller provides an internal isolation switch which allows the connection of two batteries. During battery backup operation the battery with the highest voltage is selected for use. If one battery should fail, the other will take over the load. The switch to a redundant battery is transparent to circuit operation and to the user. A battery status warning will occur when the battery in use falls below 2.0 volts. A grounded V pin will not activate a battery-fail warning. In applications where battery BAT2 redundancy is not required, a single battery should be connected to the BAT1 pin, and the BAT2 battery pin must be grounded. The nonvolatile controller contains circuitry to turn off the battery backup. This is to maintain the battery(s) at its highest capacity until the equipment is powered up and valid data is written to the SRAM. While in the freshness seal mode the CEO and V will be forced to V . When CCO OL the batteries are first attached to one or both of the V pins, V will not provide battery back-up until BAT CCO V exceeds V , as set by the TOL pin, and then falls below V . CCI CCTP BAT Figure 1 shows a typical application incorporating the DS1210 in a microprocessor-based system. Section A shows the connections necessary to write protect the RAM when V is less than 4.75 volts and to back CC up the supply with batteries. Section B shows the use of the DS1210 to halt the processor when V is CC less than 4.75 volts and to delay its restart on power-up to prevent spurious writes. 2 of 8