DS1231/S DS1231/S Power Monitor Chip FEATURES PIN ASSIGNMENT Warns processor of an impending power failure 1 8 IN VCC Provides time for an orderly shutdown NMI 2 7 MODE Prevents processor from destroying nonvolatile 3 RST 6 TOL memory during power transients 4 5 RST GND Automatically restarts processor after power is DS1231 8Pin DIP restored (300 MIL) See Mech. Drawings Suitable for linear or switching power supplies Section Adjusts to hold time of the power supply NC NC 1 16 15 VCC IN 2 Supplies necessary signals for processor interface NC NC 3 14 MODE 13 NMI 4 Accurate 5% or 10% V monitoring CC 5 NC NC 12 Replaces power-up reset circuitry TOL 6 11 RST 7 10 NC NC No external capacitors required GND 9 8 RST Optional 16-pin SOIC surface mount package DS1231S 16Pin SOIC (300 MIL) See Mech. Drawings Section PIN DESCRIPTION IN Input MODE Selects input pin characteristics TOL Selects 5% or 10% V detect CC GND Ground RST Reset (Active High) RST Reset (Active Low, open drain) NMI NonMaskable Interrupt V +5V Supply CC NC No Connections DESCRIPTION The DS1231 Power Monitor Chip uses a precise tem- shutdown is directly proportional to the available perature-compensated reference circuit which provides hold-up time of the power supply. Just before the an orderly shutdown and an automatic restart of a pro- hold-up time is exhausted, the Power Monitor uncondi- cessor-based system. A signal warning of an impending tionally halts the processor to prevent spurious cycles power failure is generated well before regulated DC by enabling Reset as V falls below a selectable 5 or CC voltages go out of specification by monitoring high volt- 10 percent threshold. When power returns, the proces- age inputs to the power supply regulators. If line isola- sor is held inactive until well after power conditions have tion is required a UL-approved opto-isolator can be di- stabilized, safeguarding any nonvolatile memory in the rectly interfaced to the DS1231. The time for processor system from inadvertent data changes. 022698 1/9DS1231/S modes of operation the input pin has hysteresis for OPERATION The DS1231 Power Monitor detects out-of-tolerance noise immunity (Figure 3). power supply conditions and warns a processor-based system of impending power failure. The main elements APPLICATION MODE PIN of the DS1231 are illustrated in Figure 1. As shown, the CONNECTED TO V CC DS1231 actually has two comparators, one for monitor- When the Mode pin is connected to V , pin 1 is a high CC ing the input (Pin 1) and one for monitoring V (Pin 8). CC impedance input. The voltage sense point and the level The V comparator outputs the signals RST (Pin 5) CC of voltage at the sense point are dependent upon the and RST (Pin 6) when V falls below a preset trip level CC application (Figure 4). The sense point may be devel- as defined by TOL (Pin 3). oped from the AC power line by rectifying and filtering the AC. Alternatively, a DC voltage level may be se- When TOL is connected to ground, the RST and RST lected which is closer to the AC power input than the signals will become active as V goes below 4.75 CC regulated +5-volt supply, so that ample time is provided volts. When TOL is connected to V , the RST and RST CC for warning before regulation is lost. signals become active as V goes below 4.5 volts. The CC RST and RST signals are excellent control signals for a Proper operation of the DS1231 requires a maximum microprocessor, as processing is stopped at the last voltage of 5 volts at the input (Pin 1), which must be possible moments of valid V . On power-up, RST and CC derived from the maximum voltage at the sense point. RST are kept active for a minimum of 150 ms to allow the This is accomplished with a simple voltage divider net- power supply to stabilize (see Figure 2). work of R1 and R2. Since the IN trip point V - is 2.3 TP volts (using the -20 device), and the maximum allowable The comparator monitoring the input pin produces the voltage on pin 1 is 5 volts, the dynamic range of voltage NMI signal (Pin 7) when the input threshold voltage at the sense point is set by the ratio of 2.3/5.0=.46 min. (V ) falls to a level as determined by Mode (Pin 2). TP This ratio determines the maximum deviation between When the Mode pin is connected to V , detection oc- CC the maximum voltage at the sense point and the actual curs at V -. In this mode Pin 1 is an extremely high im- TP voltage which will generate NMI. pedance input allowing for a simple resistor voltage di- vider network to interface with high voltage signals. Having established the desired ratio, and confirming When the Mode pin is connected to ground, detection that the ratio is greater than .46 and less than 1, the occurs at V +. In this mode Pin 1 sources 30 A of cur- TP proper values for R1 and R2 can be determined by the rent allowing for connection to switched inputs, such as equation as shown in Figure 4. A simple approach to a UL-approved opto-isolator. The flexibility of the input solving this equation is to select a value for R2 which is pin allows for detection of power loss at the earliest point high enough impedance to keep power consumption in a power supply system, maximizing the amount of low, and solve for R1. Figure 5 illustrates how the time allotted between NMI and RST. On power-up, NMI DS1231 can be interfaced to the AC power line when is released as soon as the input threshold voltage (V ) TP the mode pin is connected to V . CC is achieved and V is within nominal limits. In both CC 022698 2/9