DS1232 MicroMonitor Chip www.maxim-ic.com FEATURES PIN ASSIGNMENT Halts and restarts an out-of-control VCC PBRST 1 8 microprocessor ST TD 2 7 Holds microprocessor in check during power transients 3 RST TOL 6 Automatically restarts microprocessor after RST GND 4 5 power failure Monitors pushbutton for external override DS1232 8-Pin DIP (300-mil) Accurate 5% or 10% microprocessor power See Mech. Drawings Section supply monitoring Eliminates the need for discrete components NC 1 16 NC PBRST 2 15 VCC Space-saving, 8-pin mini-DIP NC 3 14 NC Optional 16-pin SOIC surface mount package TD 4 13 ST Industrial temperature -40C to +85C NC 5 12 NC available, designated N TOL 6 11 RST NC 7 10 NC GND 8 9 RST DS1232S 16-Pin SOIC (300-mil) See Mech. Drawings Section PIN DESCRIPTION PBRST - Pushbutton Reset Input TD - Time Delay Set TOL - Selects 5% or 10% V Detect CC GND - Ground RST - Reset Output (Active High) RST - Reset Output (Active Low, open drain) ST - Strobe Input V - +5 Volt Power CC NC - No Connections DESCRIPTION The DS1232 MicroMonitor Chip monitors three vital conditions for a microprocessor: power supply, software execution, and external override. First, a precision temperature-compensated reference and comparator circuit monitors the status of V . When an out-of-tolerance condition occurs, an internal CC power fail signal is generated which forces reset to the active state. When V returns to an in-tolerance CC condition, the reset signals are kept in the active state for a minimum of 250 ms to allow the power supply and processor to stabilize. MicroMonitor is a trademark of Dallas Semiconductor. 1 of 7 111899 DS1232/DS1232S The second function the DS1232 performs is pushbutton reset control. The DS1232 debounces the pushbutton input and guarantees an active reset pulse width of 250 ms minimum. The third function is a watchdog timer. The DS1232 has an internal timer that forces the reset signals to the active state if the strobe input is not driven low prior to timeout. The watchdog timer function can be set to operate on timeout settings of approximately 150 ms, 600 ms, and 1.2 seconds. OPERATION - POWER MONITOR The DS1232 detects out-of-tolerance power supply conditions and warns a processor-based system of impending power failure. When V falls below a preset level as defined by TOL (Pin 3), the V CC CC comparator outputs the signals RST (Pin 5) and RST (Pin 6). When TOL is connected to ground, the RST and RST signals become active as V falls below 4.75 volts. When TOL is connected to V , the RST CC CC and RST signals become active as V falls below 4.5 volts. The RST and RST are excellent control CC signals for a microprocessor, as processing is stopped at the last possible moments of valid V . On CC power-up, RST and RST are kept active for a minimum of 250 ms to allow the power supply and processor to stabilize. OPERATION - PUSHBUTTON RESET The DS1232 provides an input pin for direct connection to a pushbutton (Figure 2). The pushbutton reset input requires an active low signal. Internally, this input is debounced and timed such that RST and RST signals of at least 250 ms minimum are generated. The 250 ms delay starts as the pushbutton reset input is released from low level. OPERATION - WATCHDOG TIMER A watchdog timer function forces RST and RST signals to the active state when the ST input is not stimulated for a predetermined time period. The time period is set by the TD input to be typically 150 ms with TD connected to ground, 600 ms with TD left unconnected, and 1.2 seconds with TD connected to V . The watchdog timer starts timing out from the set time period as soon as RST and RST are inactive. CC If a high-to-low transition occurs on the ST input pin prior to timeout, the watchdog timer is reset and begins to timeout again. If the watchdog timer is allowed to timeout, then the RST and RST signals are driven to the active state for 250 ms minimum. The ST input can be derived from microprocessor address signals, data signals, and/or control signals. When the microprocessor is functioning normally, these signals would, as a matter of routine, cause the watchdog to be reset prior to timeout. To guarantee that the watchdog timer does not timeout, a high-to-low transition must occur at or less than the minimum shown in Table 1. A typical circuit example is shown in Figure 3. 2 of 7