DS1267 Dual Digital Potentiometer Chip www.dalsemi.com FEATURES PIN ASSIGNMENT Ultra-low power consumption, quiet, pumpless design VB 1 16 V CC Two digitally controlled, 256-position NC 2 15 NC potentiometers H1 3 14 S OUT Serial port provides means for setting and L1 4 13 W0 reading both potentiometers Resistors can be connected in series to W1 5 12 H0 provide increased total resistance RST 6 11 L0 14-pin DIP, 16-pin SOIC, 20-pin TSSOP CLK 7 10 C OUT packages GND 8 9 DQ Resistive elements are temperature compensated to 0.3 LSB relative linearity 16-Pin SOIC (300-mil) Standard resistance values: See Mech. Drawings Section DS1267-10 ~ 10 k DS1267-50 ~ 50 k VB 1 14 V CC DS1267-100 ~ 100 k H1 2 13 S OUT Operating Temperature Range: L1 3 12 W0 Industrial: -40C to +85C W1 4 11 H0 PIN DESCRIPTIONS RST 5 10 L0 L0, L1 - Low End of Resistor CLK 6 9 C OUT H0, H1 - High End of Resistor GND 7 8 DQ W0, W1 - Wiper Terminal of Resistor V - Substrate Bias Voltage B 14-Pin DIP (300-mil) S - Stacked Configuration Output OUT See Mech. Drawings Section RST - Serial Port Reset Input DQ - Serial Port Data Input VB 1 20 V CC CLK - Serial Port Clock Input NC 2 19 NC C - Cascade Port Output OUT H1 3 18 NC V - +5 Volt Supply CC GND - Ground L1 4 17 S OUT NC - No Internal Connection W1 5 16 W0 RST 6 15 H0 CLK 7 14 L0 NC 8 13 C OUT NC 9 12 NC GND 10 11 DQ 20-Pin TSSOP (173-mil) 1 of 12 102199DS1267 DESCRIPTION The DS1267 Dual Digital Potentiometer Chip consists of two digitally controlled, solid-state potentiometers. Each potentiometer is composed of 256 resistive sections. Between each resistive section and both ends of the potentiometer are tap points which are accessible to the wiper. The position of the wiper on the resistive array is set by an 8-bit value that controls which tap point is connected to the wiper output. Communication and control of the device are accomplished via a 3-wire serial port interface. This interface allows the device wiper position to be read or written. Both potentiometers can be connected in series (or stacked) for an increased total resistance with the same resolution. For multiple-device, single-processor environments, the DS1267 can be cascaded or daisy-chained. This feature provides for control of multiple devices over a single 3-wire bus. The DS1267 is offered in three standard resistance values which include 10, 50, and 100-kohm versions. Available packages for the device include a 14-pin DIP, 16-pin SOIC, and 20-pin TSSOP. OPERATION The DS1267 contains two 256-position potentiometers whose wiper positions are set by an 8-bit value. These two 8-bit values are written to a 17-bit I/O shift register that is used to store the two wiper positions and the stack select bit when the device is powered. A block diagram of the DS1267 is presented in Figure 1. Communication and control of the DS1267 are accomplished through a 3-wire serial port interface that drives an internal control logic unit. The 3-wire serial interface consists of the three input signals: RST , CLK, and DQ. The RST control signal is used to enable the 3-wire serial port operation of the device. The chip is selected when RST is high RST must be high to begin any communication to the DS1267. The CLK signal input is used to provide timing synchronization for data input and output. The DQ signal line is used to transmit potentiometer wiper settings and the stack select bit configuration to the 17-bit I/O shift register of the DS1267. Figure 9(a) presents the 3-wire serial port protocol. As shown, the 3-wire port is inactive when the RST signal input is low. Communication with the DS1267 requires the transition of the RST input from a low state to a high state. Once the 3-wire port has been activated, data is entered into the part on the low to high transition of the CLK signal inputs. Three-wire serial timing requirements are provided in the timing diagrams of Figure 9(b)-(c). Data written to the DS1267 over the 3-wire serial interface is stored in the 17-bit I/O shift register (see Figure 2). The 17-bit I/O shift register contains both 8-bit potentiometer wiper position values and the stack select bit. The composition of the I/O shift register is presented in Figure 2. Bit 0 of the I/O shift register contains the stack select bit, which will be discussed in the section entitledStacked Configuration Bits 1 through 8 of the I/O shift register contain the potentiometer-1 wiper position value. Bit 1 contains the MSB of the wiper setting for potentiometer-1 and bit 8 the LSB for the wiper setting. Bits 9 through 16 of the I/O shift register contain the value of the potentiometer-0 wiper position, with the MSB for the wiper position occupying bit 9 and the LSB bit 16. 2 of 12 102199