DS1267B Dual Digital Potentiometer FEATURES PIN ASSIGNMENT Two digitally controlled, 256-position potentiometers VB 1 16 V CC Serial port provides means for setting and NC 2 15 NC reading both potentiometers Resistors can be connected in series to H1 3 14 S OUT provide increased total resistance L1 4 13 W0 16-pin SO and 20-pin TSSOP packages W1 5 12 H0 Resistive elements are temperature RST 6 11 L0 compensated to 0.3 LSB relative linearity Standard resistance values: CLK 7 10 C OUT DS1267B-10 ~ 10k GND 8 9 DQ DS1267B-50 ~ 50k 16-Pin SO (300-mil) DS1267B-100 ~ 100k See Mech. Drawings Section Operating Temperature Range: Industrial: -40C to +85C PIN DESCRIPTIONS VB 1 20 V L0, L1 - Low End of Resistor CC H0, H1 - High End of Resistor NC 2 19 NC W0, W1 - Wiper Terminal of Resistor H1 3 18 NC V - Substrate Bias Voltage B L1 4 17 S OUT S - Stacked Configuration Output OUT W1 5 16 W0 RST - Serial Port Reset Input DQ - Serial Port Data Input RST 6 15 H0 CLK - Serial Port Clock Input CLK 7 14 L0 C - Cascade Port Output OUT NC 8 13 C OUT V - +5V Supply CC NC 9 12 NC GND - Ground GND 10 11 DQ NC - No Internal Connection 20-Pin TSSOP (173-mil) PIN- END-TO-END PART NO. PACKAGE RESISTANCE (k) DS1267BE-010+ 20 TSSOP 10 DS1267BE-050+ 20 TSSOP 50 DS1267BE-100+ 20 TSSOP 100 DS1267BS-010+ 16 SO 10 DS1267BS-050+ 16 SO 50 DS1267BS-100+ 16 SO 100 19-6589 Rev 1 1/14 Maxim Integrated 1 DS1267B DESCRIPTION The DS1267B Dual Digital Potentiometer Chip consists of two digitally controlled, solid-state potentiometers. Each potentiometer is composed of 256 resistive sections. Between each resistive section and both ends of the potentiometer are tap points which are accessible to the wiper. The position of the wiper on the resistive array is set by an 8-bit value that controls which tap point is connected to the wiper output. Communication and control of the device are accomplished via a 3-wire serial port interface. This interface allows the device wiper position to be read or written. Both potentiometers can be connected in series (or stacked) for an increased total resistance with the same resolution. For multiple-device, single-processor environments, the DS1267B can be cascaded or daisy-chained. This feature provides for control of multiple devices over a single 3-wire bus. The DS1267B is offered in three standard resistance values which include 10k, 50k, and 100k versions. Available packages for the device include a 16-pin SO and 20-pin TSSOP. OPERATION The DS1267B contains two 256-position potentiometers whose wiper positions are set by an 8-bit value. These two 8-bit values are written to a 17-bit I/O shift register that is used to store the two wiper positions and the stack select bit when the device is powered. A block diagram of the DS1267B is presented in Figure 1. Communication and control of the DS1267B are accomplished through a 3-wire serial port interface that drives an internal control logic unit. The 3-wire serial interface consists of the three input signals: RST , CLK, and DQ. The RST control signal is used to enable the 3-wire serial port operation of the device. The chip is selected when RST is high RST must be high to begin any communication to the DS1267B. The CLK signal input is used to provide timing synchronization for data input and output. The DQ signal line is used to transmit potentiometer wiper settings and the stack select bit configuration to the 17-bit I/O shift register of the DS1267B. Figure 9(a) presents the 3-wire serial port protocol. As shown, the 3-wire port is inactive when the RST signal input is low. Communication with the DS1267B requires the transition of the RST input from a low state to a high state. Once the 3-wire port has been activated, data is entered into the part on the low to high transition of the CLK signal inputs. Three-wire serial timing requirements are provided in the timing diagrams of Figure 9(b)-(c). Data written to the DS1267B over the 3-wire serial interface is stored in the 17-bit I/O shift register (see Figure 2). The 17-bit I/O shift register contains both 8-bit potentiometer wiper position values and the stack select bit. The composition of the I/O shift register is presented in Figure 2. Bit 0 of the I/O shift register contains the stack select bit, which will be discussed in the section entitled Stacked Configuration. Bits 1 through 8 of the I/O shift register contain the potentiometer-1 wiper position value. Bit 1 contains the MSB of the wiper setting for potentiometer-1 and bit 8 the LSB for the wiper setting. Bits 9 through 16 of the I/O shift register contain the value of the potentiometer-0 wiper position, with the MSB for the wiper position occupying bit 9 and the LSB bit 16.