19-5212 Rev 4/10 DS1705/DS1706 3.3V and 5.0V MicroMonitor www.maxim-ic.com FEATURES PIN ASSIGNMENT Halts and restarts an out-of-control WDS PBRST 1 8 microprocessor 2 V 7 RST CC Holds microprocessor in check during power transients GND 3 6 ST Automatically restarts microprocessor after NMI 4 5 IN power failure 8-Pin DIP (300 -mil) Monitors pushbutton for external override Accurate 5%, 10% or 20% resets for 3.3V WDS 1 8 PBRST systems and 5% or 10% resets for 5.0V V 2 7 RST(*RST) CC systems GND 3 6 ST Eliminates the need for discrete components NMI IN 4 5 3.3V 20% tolerance for use with 3.0V 8-Pin SOIC (150-mil) systems Pin-compatible with the MAXIM RST(*RST) ST 1 8 MAX705/MAX706 in 8-pin DIP, 8-pin SOIC, WDS 2 7 NMI PBRST 3 6 IN and -SOP V 4 5 GND CC 8-pin DIP, 8-pin SOIC and 8-pin -SOP 8-Pin -SOP (118-mil) packages See Mech. Drawings Section on website Industrial temperature range -40C to +85C DS1705 and DS1706 R/S/T (*DS1706L and DS1706P) PIN DESCRIPTION PBRST - Pushbutton Reset Input V - Power Supply CC GND - Ground IN - Input NMI - Non-maskable Interrupt ST - Strobe Input RST - Active Low Reset Output *RST - Active High Reset Output (DS1706P and DS1706L only) WDS - Watchdog Status Output DESCRIPTION The DS1705/DS1706 3.3- or 5.0-Volt MicroMonitor monitors three vital conditions for a microprocessor: power supply, software execution, and external override. A precision temperature compensated reference and comparator circuit monitor the status of V at the device and at an upstream point for maximum CC protection. When the sense input detects an out-of-tolerance condition, a non-maskable interrupt is generated. As the voltage at the device degrades, an internal power fail signal is generated which forces 1 of 12 DS1705/DS1706 the reset to an active state. When V returns to an in-tolerance condition, the reset signal is kept in the CC active state for a minimum of 130 ms to allow the power supply and processor to stabilize. The second function the DS1705/DS1706 performs is pushbutton reset control. The DS1705/DS1706 debounces the pushbutton input and guarantees an active reset pulse width of 130 ms minimum. The third function is a watchdog timer. The DS1705/DS1706 has an internal timer that forces the WDS output signal to the active state if the strobe input is not driven low prior to time-out. OPERATION Power Monitor The DS1705/DS1706 detects out-of-tolerance power supply conditions and warns a processor-based system of impending power failure. When V falls below the minimum V tolerance, a comparator CC CC outputs the RST (or RST) signal. RST (or RST) is an excellent control signal for a microprocessor, as processing is stopped at the last possible moment of valid V . On power-up, RST (or RST) are kept CC active for a minimum of 130 ms to allow the power supply and processor to stabilize. Pushbutton Reset The DS1705/DS1706 provides an input pin for direct connection to a pushbutton reset (see Figure 2). The pushbutton reset input requires an active low signal. Internally, this input is debounced and timed such that a RST (or RST) signal of at least 130 ms minimum will be generated. The 130 ms delay commences as the pushbutton reset input is released from the low level. The pushbutton can be initiated by connecting the WDS or NMI outputs to the PBRST input as shown in Figure 3. Non-Maskable Interrupt The DS1705/DS1706 generates a non-maskable interrupt ( NMI ) for early warning of a power failure. A precision comparator monitors the voltage level at the IN pin relative to an on-chip reference generated by an internal band gap. The IN pin is a high impedance input allowing for a user-defined sense point. An external resistor voltage divider network (Figure 5) is used to interface with high voltage signals. This sense point may be derived from a regulated supply or from a higher DC voltage level closer to the main system power input. Since the IN trip point V is 1.25 volts, the proper values for R1 and R2 can be TP determined by the equation as shown in Figure 5. Proper operation of the DS1705/DS1706 requires that the voltage at the IN pin be limited to V . Therefore, the maximum allowable voltage at the supply being CC monitored (V ) can also be derived as shown in Figure 5. A simple approach to solving the equation is MAX to select a value for R2 high enough to keep power consumption low, and solve for R1. The flexibility of the IN input pin allows for detection of power loss at the earliest point in a power supply system, maximizing the amount of time for system shutdown between NMI and RST (or RST). When the supply being monitored decays to the voltage sense point, the DS1705/DS1706 pulses the NMI NMI output to the active state for a minimum 200 s. The power-fail detection circuitry also has built-in hysteresis of 100 V. The supply must be below the voltage sense point for approximately 5 s before a low NMI will be generated. In this way, power supply noise is removed from the monitoring function, preventing false interrupts. During a power-up, any detected IN pin levels below V by the comparator TP are disabled from generating an interrupt until V rises to V . As a result, any potential NMI pulse CC CCTP will not be initiated until V reaches V . CC CCTP Connecting NMI to PBRST would allow non-maskable interrupt to generate an automatic reset when an out-of-tolerance condition occurred in a monitored supply. An example is shown in Figure 3. 2 of 12