DS1707/DS1708 3.3 and 5.0-Volt MicroMonitor www.maxim-ic.com FEATURES PIN ASSIGNMENT Holds microprocessor in check during power RST PBRST 1 8 transients 2 VCC 7 RST Automatically restarts microprocessor after power failure GND 3 6 NC Monitors pushbutton for external override NMI 4 5 IN Accurate 5%, 10% or 20% resets for 3.3V 8-Pin DIP (300-mil) systems and 5% or 10% resets for 5.0V systems RST 1 8 PBRST Eliminates the need for discrete components V 2 7 RST CC 20% tolerance compatible with 3.0V systems 3 6 GND NC Pin compatible with the MAXIM NMI IN 4 5 MAX707/MAX708 in 8-pin DIP, 8-pin SOIC 8-Pin SOIC (150-mil) packages 8-pin DIP, 8-pin and -SOP SOIC and 8-pin RST NC 1 8 -SOP packages available RST 2 7 NMI PBRST 3 6 IN Industrial temperature range -40 C to +85 C V 4 5 GND CC 8-Pin -SOP (118-mil) See Mech. Drawings Section on website DS1707 and DS1708 R/S/T PIN DESCRIPTION PBRST - Pushbutton Reset Input V - Power Supply CC GND - Ground IN - Input NMI - Non-maskable Interrupt NC - No Connect RST - Active Low Reset Output RST - Active High Reset Output DESCRIPTION The DS1707/DS1708 3.3- or 5.0-Volt MicroMonitor monitors three vital conditions for a microprocessor: power supply, voltage sense, and external override. A precision temperature-compensated reference and comparator circuit monitor the status of V at the device and at an upstream point for maximum CC protection. When the sense input detects an out-of-tolerance condition a non-maskable interrupt is generated. As the voltage at the device degrades an internal power fail signal is generated which forces the reset to an active state. When V returns to an in-tolerance condition, the reset signal is kept in the CC active state for a minimum of 130 ms to allow the power supply and processor to stabilize. 1 of 10 041305 DS1707/DS1708 The third function the DS1707/DS1708 performs is pushbutton reset control. The DS1707/DS1708 debounces the pushbutton input and guarantees an active reset pulse width of 130 ms minimum. OPERATION Power Monitor The DS1707/DS1708 detects out-of-tolerance power supply conditions and warns a processor-based system of impending power failure. When V falls below the minimum V tolerance, a comparator CC CC outputs the RST and RST signals. RST and RST are excellent control signals for a microprocessor, as processing is stopped at the last possible moment of valid V . On power-up, RST and RST are kept CC active for a minimum of 130 ms to allow the power supply and processor to stabilize. Pushbutton Reset The DS1707/DS1708 provides an input pin for direct connection to a pushbutton reset (see Figure 2). The pushbutton reset input requires an active low signal. Internally, this input is debounced and timed such that RST and RST signals of at least 130 ms minimum will be generated. The 130 ms delay commences as the pushbutton reset input is released from the low level. The pushbutton can be initiated by connecting the NMI output to the PBRST input as shown in Figure 3. Non-Maskable Interrupt The DS1707/DS1708 generates a non-maskable interrupt ( NMI ) for early warning of a power failure. A precision comparator monitors the voltage level at the IN pin relative to an on-chip reference generated by an internal band gap. The IN pin is a high impedance input allowing for a user-defined sense point. An external resistor voltage divider network (Figure 5) is used to interface with high voltage signals. This sense point may be derived from a regulated supply or from a higher DC voltage level closer to the main system power input. Since the IN trip point V is 1.25 volts, the proper values for R1 and R2 can be TP determined by the equation as shown in Figure 5. Proper operation of the DS1707/DS1708 requires that the voltage at the IN pin be limited to V . Therefore, the maximum allowable voltage at the supply being CC monitored (V ) can also be derived as shown in Figure 5. A simple approach to solving the equation is MAX to select a value for R2 high enough to keep power consumption low, and solve for R1. The flexibility of the IN input pin allows for detection of power loss at the earliest point in a power supply system, maximizing the amount of time for system shut-down between NMI and RST/ RST . When the supply being monitored decays to the voltage sense point, the DS1707/DS1708 pulses the NMI output to the active state for a minimum 200 s. The NMI power-fail detection circuitry also has built-in hysteresis of 100 V. The supply must be below the voltage sense point for approximately 5 s before a low NMI will be generated. In this way, power supply noise is removed from the monitoring function, preventing false interrupts. During a power-up, any detected IN pin levels below V by the comparator TP are disabled from generating an interrupt until V rises to V . As a result, any potential NMI pulse CC CCTP will not be initiated until V reaches V . CC CCTP Connecting NMI to PBRST would allow the non-maskable interrupt to generate an automatic reset when an out-of-tolerance condition occurred in a monitored supply. An example is shown in Figure 3. 2 of 10