DS1803 Addressable Dual Digital Potentiometer www.maxim-ic.com FEATURES PIN ASSIGNMENT 3V or 5V Operation Ultra-Low Power Consumption H1 1 14 VCC Two Digitally Controlled, 256-Position L1 2 13 NC Potentiometers W1 3 12 H0 14-Pin TSSOP (173 mil) and 16-Pin SO (150 A2 4 11 L0 mil) Packaging Available for Surface-Mount A1 5 10 W0 Applications A0 6 9 SDA Addressable Using 3 Address Inputs GND 7 8 SCL 2-Wire Serial Interface Operating Temperature Range: DS1803 14-PIN TSSOP (173 MIL) - Industrial: -40C to +85C Standard Resistance Values: - DS1803-010 10k - DS1803-050 50k H1 1 16 VCC - DS1803-100 100k NC 2 15 NC L1 3 14 H0 W1 4 13 L0 A2 5 12 W0 PIN DESCRIPTION A1 6 11 NC L0, L1 - Low End of Resistor A0 7 10 SDA H0, H1 - High End of Resistor W0,W1 - Wiper terminal of Resistor GND 8 9 SCL V - 3V/5V Power Supply Input CC A0, A1, A2 - Chip Select Inputs DS1803Z 16-PIN SO (150 MIL) SDA - Serial Data I/O DS1803 16-PIN DIP (300 MIL) See Mech. Drawings Section on Website SCL - Serial Clock Input GND - Ground NC - No Connection DESCRIPTION The DS1803 addressable dual digital potentiometer features two independently controlled 256-position potentiometers. Device control is achieved through a 2-wire serial interface. Three address pins allow up to 8 DS1803s to share the same 2-wire interface. The exact wiper position of each potentiometer can be written or read. The DS1803 is available in a 16-pin DIP, 16-pin SO, and 14-pin TSSOP package. The device is available in three standard resistance values: 10k, 50k, and 100k and is specified over the industrial temperature range. 1 of 11 110706 DS1803 DEVICE OPERATION The DS1803 is an addressable, digitally controlled device which has two 256-position potentiometers. A functional block diagram of the part is shown in Figure 1. Communication and control of the device is accomplished via a 2-wire serial interface. Address inputs A0, A1, and A2 allow up to 8 DS1803s to share the same 2-wire interface. Each potentiometer is composed of a 256 position resistor array. Two 8-bit registers, each assigned to a respective potentiometer, are used to set the wiper position on the resistor array. The wiper terminal is multiplexed to one of 256 positions on the resistor array based on its corresponding 8-bit register value. For example, the high-end terminals, H0 and H1, have wiper position values FFh while the low-end terminals, L0 and L1, have wiper position values 00h. The DS1803 is a volatile device that does not maintain the position of the wiper during power-down or loss of power. On power-up, the DS1803 wipers position will be set to position 00h - the low-end terminals. The user may then set the wiper value to a desired position. Communication with the DS1803 takes place over the 2-wire serial interface consisting of the bi- directional pin, SDA, and the serial clock input, SCL. Complete details of the 2-wire interface are discussed in the section entitled 2-wire Serial Data Bus. Application Considerations The DS1803 is offered in three standard resistor values, which include 10k, 50k, and 100k. The resolution of the potentiometer is defined as R /255, where R is the total resistor value of the TOT TOT potentiometer. The DS1803 is designed to operate using 3V or 5V power supplies over the industrial (-40C to +85C) temperature range. Maximum input signal levels across the potentiometer cannot exceed the operating power supply of the device. 2-WIRE SERIAL DATA BUS The DS1803 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are slaves. The bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The DS1803 operates as a slave on the 2-wire bus. Connections to the bus are made via the open-drain I/O lines SDA and SCL. The following bus protocol has been defined (see Figure 2). Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is high will be interpreted as control signals. Accordingly, the following bus conditions have been defined: Bus not busy: Both data and clock lines remain HIGH. Start data transfer: A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. 2 of 11