DS1867 Dual Digital Potentiometer with EEPROM www.dalsemi.com FEATURES PIN ASSIGNMENT Nonvolatile version of the popular DS1267 Low power consumption, quiet, pumpless V 1 14 V B CC design H1 2 13 S OUT L1 3 12 WO Operates from single 5V or 5V supplies Two digitally controlled, 256-position W1 4 11 HO potentiometers RST 5 10 LO Wiper position is maintained in the absence of CLK 6 9 C OUT power GND 7 8 DQ Serial port provides means for setting and 14-Pin DIP (300-mil) reading both potentiometers See Mech. Drawings Section Resistors can be connected in series to provide increased total resistance 16-pin SOIC and 20-pin TSSOP for surface V 1 16 V B CC mount applications NC 2 15 NC Standard resistance values: H1 3 14 S OUT - DS1867-10 ~ 10 k L1 4 13 WO - DS1867-50 ~ 50 k W1 5 12 HO - DS1867-100 ~ 100 k RST 6 11 LO Operating Temperature Range: CLK 7 10 C OUT - Industrial: -40 C to +85C GND 8 9 DQ 16-Pin SOIC (300-mil) PIN DESCRIPTION See Mech. Drawings Section L0, L1 - Low End of Resistor H0, H1 - High End of Resistor V 1 20 V B CC W1, W2 - Wiper End of Resistor NC 2 19 DNC V - Substrate Bias B H1 3 18 DNC S - Wiper for Stacked Configuration OUT L1 4 17 S OUT RST - Serial Port Reset Input W1 5 16 WO DQ - Serial Port Data Input RST 6 15 HO CLK - Serial Port Clock Input CLK 7 14 LO C - Cascade Serial Port Output OUT DNC 8 13 C OUT V - +5-Volt Supply Input CC DNC 9 12 DNC GND - Ground GND 10 11 DQ NC - No Internal Connection 20-Pin TSSOP (173-mil) DNC - Do Not Connect See Mech. Drawings Section 1 of 14 102199DS1867 DESCRIPTION The DS1867 Dual Digital Potentiometer with EEPROM is the nonvolatile version of the popular DS1267 Dual Digital Potentiometer. The DS1867 consists of two digitally controlled potentiometers having 256- position wiper settings. Wiper position is maintained in the absence of power through the use of EEPROM memory cell arrays. Communication and control of the device are accomplished over a 3-wire serial port which allows reads and writes of the wiper position. Both potentiometers can be stacked for increased total resistance with the same resolution. For multiple-device, single-processor environments, the DS1867 can be cascaded for control over a single 3-wire bus. The DS1867 is offered in three standard resistance values. OPERATION The DS1867 contains two 256-position potentiometers whose wiper positions are set by an 8-bit value. These two 8-bit values are written to a 17-bit I/O shift register which is used to store wiper position and the stack select bit when the device is powered. An additional memory area, the shadow memory, stores the 17-bit I/O shift register during a power-down sequence which provides for wiper nonvolatility. A block diagram of the DS1867 is presented in Figure 1. Communication and control of the DS1867 is accomplished through a 3-wire serial port interface that drives an internal control logic unit. The 3-wire serial interface consists of the three input signals: RST , CLK, and DQ. The RST control signal is used to enable 3-wire serial port operation of the device. The RST signal is an active high input and is required to begin any communication to the DS1867. The CLK signal input is used to provide timing synchronization for data input and output. The DQ signal line is used to transmit potentiometer wiper settings and the stack select bit configuration to the 17-bit I/O shift register of the DS1867. Figure 2(a) presents the 3-wire serial port protocol. As shown, the 3-wire port is inactive when the RST signal input is low. Communication with the DS1867 requires the transition of the RST input from a low state to a high state. Once the 3-wire port has been activated, data is latched into the part on the low to high transition of the CLK signal input. Three-wire serial timing requirements are provided in the timing diagrams of Figure 2(b) and (c). Data written to the DS1867 over the 3-wire serial interface is stored in the 17-bit I/O shift register (see Figure 3). The 17-bit I/O shift register contains both 8-bit potentiometer wiper position values and the stack select bit. The composition of the I/O shift register is presented in Figure 3. Bit 0 of the I/O shift register contains the stack select bit. This bit will be discussed in the section entitled Stacked Configuration. Bits 1 through 8 of the I/O shift register contain the potentiometer-1 wiper position value. Bit 1 will contain the MSB of the wiper setting for potentiometer-1 and bit 8 the LSB for the wiper setting. Bits 9 through 16 of the I/O shift register contain the value of the potentiometer-0 wiper position with the MSB for the wiper position occupying bit 9 and the LSB bit 16. 2 of 14 102199