DS1868B Dual Digital Potentiometer www. maximintegrated.com FEATURES PIN ASSIGNMENT Two digitally controlled, 256-position potentiometers V VB 1 20 CC Serial port provides means for setting and DNC DNC 2 19 reading both potentiometers DNC H1 3 18 Resistors can be connected in series to S L1 4 17 OUT provide increased total resistance W0 W1 5 16 20-pin TSSOP and 16-pin SO packages are H0 RST 6 15 L0 available CLK 7 14 C OUT Resistive elements are temperature DNC 8 13 DNC DNC 9 12 compensated to 0.3 LSB relative linearity DQ GND 10 11 Standard resistance values: 20-Pin TSSOP (173-mil) - DS1868B-10 ~10kW - DS1868B-50 ~50kW VB 1 16 VCC - DS1868B-100 ~100kW NC 2 15 NC +5V or 3V operation H1 S 3 14 OUT L1 4 13 W0 Operating temperature range: W1 5 12 H0 Industrial: -40C to +85C RST 6 11 L0 CLK 7 10 C OUT GND 8 9 DQ PIN DESCRIPTION DS1868BS 16-Pin SO (300-mil) L0, L1 - Low End of Resistor H0, H1 - High End of Resistor W0, W1 - Wiper Terminal of Resistor S - Stacked Configuration Output OUT RST - Serial Port Reset Input END-TO-END DQ - Serial Port Data Input PIN- PART NO. RESISTANCE CLK - Serial Port Clock Input PACKAGE (k) C - Cascade Port Output OUT DS1868BE-010+ 20 TSSOP 10 V - +5 Volt Supply CC DS1868BE-050+ 20 TSSOP 50 GND - Ground Connections DS1868BE-100+ 20 TSSOP 100 NC - No Internal Connection DS1868BS-010+ 16 SO 10 V - Substrate Bias Voltage B DS1868BS-050+ 16 SO 50 DNC - Do Not Connect DS1868BS-100+ 16 SO 100 *All GND pins must be connected to ground. 19-6593 Rev 1 1/14 Maxim Integrated 1 DS1868B DESCRIPTION The DS1868B Dual Digital Potentiometer Chip consists of two digitally contro-llestatde solid potentiometers. Each potentiometer is composed of 256 resistive sections. Between each resistive section and both ends of the potentiometer are tap points which are accessible to the wiper. The position of the wiper on the resistor array is set by an 8bi- t value that controls which tap point is connected to the wiper output. Communication and control of the device is accomplished via a 3w- ire serial port interface. This interface allows the device wiper position to be read or written. Both potentiometers can be connected in series (or stacked) for an increased total resistance with the same resolution. For multiple-device, single-processor environments, the DS1868B can be cascaded or daisy chained. This feature provides for control of multiple devices over a single 3-wire bus. The DS1868B is offered in three standard resistance values which include 10, k50k, and 100k versions. The part is available in 16-pin SO (300-mil) and 20-pin (173-mil) TSSOP packages. OPERATION The DS1868B contains two 256-position potentiometers whose wiper positions are set by an 8bi- t value. These two 8-bit values are written to a 1-b7it I/O shift register which is used to store the two wiper positions and the stack select bit when the device is powered. A block diagram of the DS1868B is presented in Figure 1. Communication and control of the DS1868B is accomplished through a -3wire serial port interface that drives an internal control logic unit. The 3w- ire serial interface consists of the three input signals: RST , CLK, and DQ. The RST control signal is used to enable the 3-wire serial port operation of the device. The RST signal is an active-high input and is required to begin any communication to the DS1868B. The CLK signal input is used to provide timing synchronization for data input and output. The DQ signal line is used to transmit potentiometer wiper settings and the stack select bit configuration to the -1b7it I/O shift register of the DS1868B. Figure 9(a) presents the 3-wire serial port protocol. As shown, the 3w- ire port is inactive when the RST signal input is low. Communication with the DS1868B requires the transition of theRS T input from a low state to a high state. Once the 3-wire port has been activated, data is entered into the part on the low to high transition of the CLK signal inputs. Thr-eweire serial timing requirements are provided in the timing diagrams of Figure 9(b),(c). Data written to the DS1868B over the 3w- ire serial interface is stored in the 17-bit I/O shift register (see Figure 2). The 17-bit I/O shift register contains both -8bit potentiometer wiper position values and the stack select bit. The composition of the I/O shift register is presented in Figure 2. Bit 0 of the I/O shift register contains the stack select bit. This bit will be discussed in the section entitled Stacked Configuration. Bits 1 through 8 of the I/O shift register contain the potentiomete-r1 wiper position value. Bit 1 will contain the MSB of the wiper setting foorte pntiometer-1 and bit 8 the LSB for the wiper setting. Bits 9 through 16 of the I/O shift register contain the value of the potentiomete-r0 wiper position with the MSB for the wiper position occupying bit 9 and the LSB bit 16. Maxim Integrated ............................................................................................................................................................................................. 2