DS21348/DS21Q348 3.3V E1/T1/J1 Line Interface www.maxim-ic.com FEATURES PIN CONFIGURATIONS 111 PRELMINARY Complete E1, T1, or J1 Line Interface Unit 44 TOP VIEW (LIU) Supports Both Long-Haul And Short-Haul 1 Trunks DS21348 Internal Software-Selectable Receive-Side Termination for 75/100/120 3.3V Power Supply 32-Bit or 128-Bit Crystal-Less Jitter Attenuator Requires Only a 2.048MHz Master Clock for Both E1 and T1 with 44 TQFP Option to Use 1.544MHz for T1 Generates the Appropriate Line Build-Outs, with and without Return loss, for E1 and DS21Q348 DSX-1 and CSU Line Build-Outs for T1 AMI, HDB3, and B8ZS, Encoding/Decoding 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz Clock Output Synthesized to Recovered Clock 49 CSBGA (7mm x 7mm) Programmable Monitor Mode for Receiver Loopbacks and PRBS Pattern Generation/ See Section 8 for 144-pin CSBGA pinout. Detection with Output for Received Errors Generates/Detects In-Band Loop Codes, 1 to 16 Bits Including CSU Loop Codes 8-Bit Parallel or Serial Interface with ORDERING INFORMATION Optional Hardware Mode TEMP PART CHANNEL PIN-PACKAGE Muxed and Nonmuxed Parallel Bus Supports RANGE Intel or Motorola DS21348TN Single -40C to +85C 44 TQFP Detects/Generates Blue (AIS) Alarms DS21348TN+ Single -40C to +85C 44 TQFP DS21348T Single 0C to +70C 44 TQFP NRZ/Bipolar Interface for Tx/Rx Data I/O DS21348T+ Single 0C to +70C 44 TQFP Transmit Open-Circuit Detection DS21348GN Single -40C to +85C 49 CSBGA Receive Carrier Loss (RCL) Indication DS21348GN+ Single -40C to +85C 49 CSBGA (G.775) DS21348G Single 0C to +70C 49 CSBGA High-Impedance State for TTIP and TRING DS21348G+ Single 0C to +70C 49 CSBGA 50mA (RMS) Current Limiter DS21Q348N Four -40C to +85C 144 CSBGA DS21Q348 Four 0C to +70C 144 CSBGA + Denotes lead-free/RoHS-compliant package. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 76 REV: 011206 DS21348/DS21Q348 DETAILED DESCRIPTION The DS21348 is a complete selectable E1 or T1 line interface unit (LIU) for short-haul and long-haul applications. Throughout the data sheet, J1 is represented wherever T1 exists. Receive sensitivity adjusts automatically to the incoming signal and can be programmed for 0dB to 12dB or 0dB to 43dB for E1 applications and 0dB to 30dB or 0dB to 36dB for T1 applications. The device can generate the necessary G.703 E1 waveshapes in 75 or 120 applications and DSX-1 line build-outs or CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB for T1 applications. The crystal-less on-board jitter attenuator requires only a 2.048MHz MCLK for both E1 and T1 applications (with the option of using a 1.544MHz MCLK in T1 applications). The jitter attenuator FIFO is selectable to either 32 bits or 128 bits in depth and can be placed in either the transmit or receive data paths. An X 2.048MHz output clock synthesized to RCLK is available for use as a backplane system clock (where n = 1, 2, 4, or 8). The DS21348 has diagnostic capabilities such as loopbacks and PRBS pattern generation/detection. 16- bit loop-up and loop-down codes can be generated and detected. The device can be controlled through an 8-bit parallel muxed or nonmuxed port, serial port, or used in hardware mode. The device fully meets all of the latest E1 and T1 specifications including ANSI T1.403-1999, ANSI T1.408, AT&T TR 62411, ITU G.703, G.704, G.706, G.736, G.775, G.823, I.431, O.151, O.161, ETSI ETS 300 166, JTG.703, JTI.431, JJ-20.1, TBR12, TBR13, and CTR4. 2 of 76