DS21352LB+ Analog Devices

3.3V DS21352 and 5V DS21552 T1 Single-Chip Transceivers www.maxim-ic.com FEATURES PIN ASSIGNMENT Complete DS1/ISDNPRI/J1 transceiver functionality Long and Short haul LIU Crystalless jitter attenuator Generates DSX1 and CSU line build-outs HDLC controller with 64-byte buffers Configurable for FDL or DS0 operation Dual twoframe elastic store slip buffers that can connect to asynchronous backplanes up to 8.192MHz DS21352 8.192MHz clock output locked to RCLK DS21552 Interleaving PCM Bus Operation Per-channel loopback and idle code insertion 8-bit parallel control port muxed or nonmuxed buses 100 (Intel or Motorola) Programmable output clocks for Fractional T1 1 Fully independent transmit and receive functionality Generates/detects in-band loop codes from 1 to 8 bits in length including CSU loop codes IEEE 1149.1 JTAG-Boundary Scan Pin compatible with DS2152/54/354/554 SCTs ORDERING INFORMATION 100-pin LQFP package (14 mm x 14 mm) 3.3V (DS21352) or 5V (DS21552) supply low power CMOS DS21352L (0 C to +70 C) DS21352LN (-40 C to +85 C) DS21552L (0 C to +70 C) DS21552LN (-40 C to +85 C) DESCRIPTION The DS21352/552 T1 single-chip transceiver contains all of the necessary functions for connection to T1 lines whether they are DS1 long haul or DSX1 short haul. The clock recovery circuitry automatically adjusts to T1 lines from 0 feet to over 6000 feet in length. The device can generate both DSX1 line build outs as well as CSU line build-outs of -7.5dB, -15dB, and -22.5dB. The onboard jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also used for extracting and inserting robbed-bit signaling data and FDL data. The device contains a set of internal registers which the user can access and control the operation of the unit. Quick access via the parallel control port allows a single controller to handle many T1 lines. The device fully meets all of the latest T1 specifications including ANSI T1.403-1995, ANSI T1.231-1993, AT&T TR 62411 (1290), AT&T TR54016, and ITU G.703, G.704, G.706, G.823, and I.431. 1 of 137 120501DS21352/DS21552 TABLE OF CONTENTS 1. LIST OF FIGURES .........................................................................................................................5 2. LIST OF TABLES ...........................................................................................................................6 3. INTRODUCTION............................................................................................................................7 3.1 FUNCTIONAL DESCRIPTION..............................................................................................8 3.2 DOCUMENT REVISION HISTORY....................................................................................10 4. PIN DESCRIPTION ......................................................................................................................11 4.1 PIN FUNCTION DESCRIPTION..........................................................................................17 4.1.1 Transmit Side Pins ........................................................................................................17 4.1.2 Receive Side Pins ..........................................................................................................20 4.1.3 Parallel Control Port Pins............................................................................................23 4.1.4 JTAG Test Access Port Pins .........................................................................................25 4.1.5 Interleave Bus Operation Pins......................................................................................25 4.1.6 Line Interface Pins........................................................................................................26 4.1.7 Supply Pins....................................................................................................................27 5. PARALLEL PORT........................................................................................................................28 5.1 REGISTER MAP ...................................................................................................................28 6. CONTROL, ID, AND TEST REGISTERS .................................................................................32 6.1 POWER-UP SEQUENCE......................................................................................................32 6.2 DEVICE ID ............................................................................................................................32 6.3 PAYLOAD LOOPBACK.......................................................................................................37 6.4 FRAMER LOOPBACK .........................................................................................................38 6.5 PULSE DENSITY ENFORCER............................................................................................40 6.6 REMOTE LOOPBACK .........................................................................................................44 7. STATUS AND INFORMATION REGISTERS..........................................................................45 8. ERROR COUNT REGISTERS....................................................................................................52 8.1 LINE CODE VIOLATION COUNT REGISTER (LCVCR) ................................................53 8.2 PATH CODE VIOLATION COUNT REGISTER (PCVCR) ...............................................54 8.3 MULTIFRAMES OUT OF SYNC COUNT REGISTER (MOSCR)....................................55 9. DSO MONITORING FUNCTION...............................................................................................56 2 of 137