DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS21354/DS213554 single-chip transceivers Complete E1 (CEPT) PCM-30/ISDN-PRI (SCTs) contain all the necessary functions to connect to Transceiver Functionality E1 lines. The devices are upward-compatible versions On-Board Long- and Short-Haul Line Interface of the DS2153 and DS2154 SCTs. The on-board for Clock/Data Recovery and Waveshaping clock/data recovery circuitry coverts the AMI/HDB3 E1 32-Bit or 128-Bit Crystal-Less Jitter Attenuator waveforms to an NRZ serial stream. Both devices Frames to FAS, CAS, CCS, and CRC4 Formats automatically adjust to E1 22AWG (0.6mm) twisted- Integral HDLC Controller with 64-Byte Buffers pair cables from 0 to over 2km in length. They can Configurable for Sa Bits, DS0, or Sub-DS0 generate the necessary G.703 waveshapes for both 75 Operation coax and 120 twisted cables. The on-board jitter Dual Two-Frame Elastic Store Slip Buffers that attenuator (selectable to either 32 bits or 128 bits) can can Connect to Asynchronous Backplanes up to be placed in either the transmit or receive data paths. 8.192MHz The framer locates the frame and multiframe Interleaving PCM Bus Operation boundaries and monitors the data stream for alarms. It is 8-Bit Parallel Control Port that can be used also used for extracting and inserting signaling data, Si, Directly on Either Multiplexed or and Sa-bit information. The on-board HDLC controller Nonmultiplexed Buses (Intel or Motorola) can be used for Sa-bit links or DS0s. The devices contain a set of internal registers that the user can Extracts and Inserts CAS Signaling access to control the operation of the units. Quick Detects and Generates Remote and AIS Alarms access through the parallel control port allows a single Programmable Output Clocks for Fractional E1, controller to handle many E1 lines. The devices fully H0, and H12 Applications meet all the latest E1 specifications, including ITU-T Fully Independent Transmit and Receive G.703, G.704, G.706, G.823, G.732, and I.431, ETS Functionality 300 011, 300 233, and 300 166, as well as CTR12 and Full Access to Si and Sa Bits Aligned with CTR4. CRC-4 Multiframe Four Separate Loopback Functions for Testing PIN CONFIGURATION Functions Large Counters for Bipolar and Code Violations, TOP VIEW CRC4 Codeword Errors, FAS Word Errors, and E Bits IEEE 1149.1 JTAG-Boundary Scan Architecture Dallas Pin Compatible with DS2154/52/352/552 SCTs Semiconductor DS21354/DS21554 3.3V (DS21354) or 5V (DS21554) Supply Low- Power CMOS 100-pin LQFP package (14mm x 14mm) ORDERING INFORMATION PART TEMP RANGE PIN-PACKAGE 100 DS21354L 0C to +70C 100 LQFP 1 DS21354LN -40C to +85C 100 LQFP LQFP DS21554L 0C to +70C 100 LQFP DS21554LN -40C to +85C 100 LQFP Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 124 REV: 021004 DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers TABLE OF CONTENTS 1. INTRODUCTION.................................................................................................................. 6 1.1. FUNCTIONAL DESCRIPTION..............................................................................................................................7 1.2. DOCUMENT REVISION HISTORY .............................................................................................................8 2. BLOCK DIAGRAM .............................................................................................................. 9 3. PIN DESCRIPTION............................................................................................................ 10 3.1. PIN FUNCTION DESCRIPTION ................................................................................................................14 3.1.1. Transmit-Side Pins..............................................................................................................................14 3.1.2. Receive-Side Pins...............................................................................................................................17 3.1.3. Parallel Control Port Pins....................................................................................................................20 3.1.4. JTAG Test Access Port Pins...............................................................................................................22 3.1.5. Interleave Bus Operation Pins ............................................................................................................22 3.1.6. Line Interface Pins ..............................................................................................................................23 3.1.7. Supply Pins .........................................................................................................................................24 4. PARALLEL PORT............................................................................................................. 25 4.1. REGISTER MAP ........................................................................................................................................25 5. CONTROL, ID, AND TEST REGISTERS .......................................................................... 30 5.1. POWER-UP SEQUENCE ..........................................................................................................................30 5.2. SYNCHRONIZATION AND RESYNCHRONIZATION...............................................................................32 5.3. FRAMER LOOPBACK ...............................................................................................................................36 5.4. AUTOMATIC ALARM GENERATION........................................................................................................38 5.5. REMOTE LOOPBACK ...............................................................................................................................40 5.6. LOCAL LOOPBACK...................................................................................................................................40 6. STATUS AND INFORMATION REGISTERS .................................................................... 43 6.1. CRC4 SYNC COUNTER............................................................................................................................45 7. ERROR COUNT REGISTERS........................................................................................... 50 7.1. BPV OR CODE VIOLATION COUNTER ...................................................................................................50 7.2. CRC4 ERROR COUNTER.........................................................................................................................51 7.3. E-BIT COUNTER .......................................................................................................................................51 7.4. FAS ERROR COUNTER.................................................................................................................................52 8. DS0 MONITORING FUNCTION ........................................................................................ 53 9. SIGNALING OPERATION................................................................................................. 56 9.1. PROCESSOR-BASED SIGNALING ..........................................................................................................56 9.2. HARDWARE-BASED SIGNALING ............................................................................................................58 9.2.1. Receive Side .......................................................................................................................................58 9.2.2. Transmit Side ......................................................................................................................................59 10. PER-CHANNEL CODE GENERATION AND LOOPBACK............................................... 60 10.1. TRANSMIT-SIDE CODE GENERATION ................................................................................................60 10.1.1. Simple Idle Code Insertion and Per-Channel Loopback.....................................................................60 10.1.2. Per-Channel Code Insertion ...............................................................................................................61 10.2. RECEIVE-SIDE CODE GENERATION...................................................................................................62 11. CLOCK BLOCKING REGISTERS..................................................................................... 63 2 of 124