DS2143/DS2143Q E1 Controller www.dalsemi.com FEATURES PIN ASSIGNMENT E1/ISDN-PRI framing transceiver 1 VDD TCLK 40 Frames to CAS, CCS, and CRC4 formats TSER 39 TSYNC 2 Parallel control port TCHCLK 3 38 TLINK 4 37 TLCLK TPOS Onboard two frame elastic store slip buffer INT1 TNEG 5 36 Extracts and inserts CAS signaling bits 6 35 INT2 AD0 Programmable output clocks for fractional E1 AD1 RLOS/LOTC 7 34 AD2 8 33 TCHBLK links, DS0 loopbacks, and drop and insert AD3 RCHBLK 9 32 applications AD4 10 31 LI CS Onboard Sa data link support circuitry AD5 LI CLK 11 30 12 29 FEBE E-Bit detection, counting and AD6 LI SDI 13 28 AD7 SYSCLK generation 14 27 RNEG BTS Pin-compatible with DS2141A T1 Controller RD(DS) 15 26 RPOS 5V supply low power (50 mW) CMOS CS 16 25 RSYNC Available in 40-pin DIP and 44-pin PLCC RSER ALE(AS) 17 24 18 23 (DS2143Q) WR(R/W) RCHCLK 19 22 RLINK RCLK VSS 20 21 RLCLK 40-Pin DIP (600-mil) 6 5 4 3 2 1 44 43 42 41 40 7 39 AD0 RLOS/LOTC 8 38 AD1 TCHBLK 9 AD2 37 RCHBLK 10 36 AD3 LI CS 11 35 AD4 LI CLK 44-PIN PLCC 12 34 AD5 LI SDI 13 AD6 33 NC 14 32 AD7 NC 15 31 BTS SYSCLK 30 16 RNEG RD(DS) 17 29 NC RPOS 18 19 20 21 22 23 24 25 26 27 28 DESCRIPTION The DS2143 is a comprehensive, software-driven E1 framer. It is meant to act as a slave or coprocessor to a microcontroller or microprocessor. Quick access via the parallel control port allows a single micro to handle many E1 lines. The DS2143 is very flexible and can be configured into numerous orientations via software. The software orientation of the device allows the user to modify their design to conform to future E1 specification changes. The controller contains a set of 69 8-bit internal registers which the user 1 of 44 112099 NC TNEG CS TPOS ALE(AS) TCHCLK TSER WR(R/W) RLINK TCLK VSS VDD RLCLK TSYNC RCLK TLINK RCHCLK TLCLK RSER INT1 RSYNC INT2DS2143/DS2143Q can access. These internal registers are used to configure the device and obtain information from the E1 link. The device fully meets al l of the latest E1 specifications, including CCITT G.704, G.706, and G.732. 1.0 INTRODUCTION The DS2143 E1 Controller has four main sections: the receive side, the transmit side, the line interface controller, and the parallel control port. See the Block Diagram. On the receive side, the device will clock in the serial E1 stream via the RPOS and RNEG pins. The synchronizer will locate the frame and multiframe patterns and establish their respective positions. This information will be used by the rest of the receive side circuitry. The DS2143 is an off-line framer, which means that all of the E1 serial stream that goes into the device will come out of it unchanged. Once the E1 data has been framed to, the signaling data can be extracted. The two-frame elastic store can either be enabled or bypassed. The transmit side clocks in the unframed E1 stream at TSER and add in the framing pattern and the signaling. The line interface control port will update line interface devices that contain a serial port. The parallel control port contains a multiplexed address and data structure which can be connected to either a microcontroller or microprocessor. Readers Note: This data sheet assumes a particular nomenclature of the E1 operating environment. There are 32 8-bit timeslots in an E1 systems which are number 0 to 31. Timeslot 0 is transmitted first and received first. These 32 timeslots are also referred to as channels with a numbering scheme of 1 to 32. Timeslot 0 is identical to channel 1, timeslot 1 is identical to channel 2, and so on. Each timeslot (or channel) is made up of 8 bits which are numbered 1 to 8. Bit number 1 is the MSB and is transmitted first. Bit number 8 is the LSB and is transmitted last. Throughout this data sheet, the following abbreviations will be used: FAS Frame Alignment Signal CRC4 Cyclical Redundancy Check CAS Channel Associated Signaling CCS Common Channel Signaling MF Multiframe Sa Additional bits Si International bits E-bit CRC4 Error Bits 2 of 44