DS2148/DS21Q48 5V E1/T1/J1 Line Interface Unit www.maxim-ic.com PIN CONFIGURATION FEATURES Complete E1, T1, or J1 Line Interface Unit TOP VIEW 44 (LIU) Supports Both Long- and Short-Haul Trunks 1 Internal Software-Selectable Receive-Side Termination for 75/100/120 DS2148 5V Power Supply 32-Bit or 128-Bit Crystal-Less Jitter Attenuator Requires Only a 2.048MHz Master Clock for Both E1 and T1 with Option to Use 1.544MHz for T1 Generates the Appropriate Line Build-Outs, 44 TQFP With and Without Return Loss, for E1 and DSX-1 and CSU Line Build-Outs for T1 DS2148 AMI, HDB3, and B8ZS, Encoding/Decoding 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz Clock Output Synthesized to Recovered Clock Programmable Monitor Mode for Receiver 49 CSBGA Loopbacks and PRBS Pattern Generation/ (7mm x 7mm) Detection with Output for Received Errors Generates/Detects In-Band Loop Codes, 1 to See Section 8 for 144-pin CSBGA pinout. 16 Bits including CSU Loop Codes 8-Bit Parallel or Serial Interface with Optional Hardware Mode ORDERING INFORMATION Multiplexed and Nonmultiplexed Parallel TEMP PIN- PART CHANNEL RANGE PACKAGE Bus Supports Intel or Motorola DS2148TN Single -40C to +85 C 44 TQFP Detects/Generates Blue (AIS) Alarms DS2148TN+ Single -40C to +85 C 44 TQFP NRZ/Bipolar Interface for Tx/Rx Data I/O DS2148T Single 0C to +70 C 44 TQFP Transmit Open-Circuit Detection DS2148T+ Single 44 TQFP Receive Carrier Loss (RCL) Indication 0C to +70 C (G.775) DS2148GN Single -40C to +85 C 49 CSBGA High-Z State for TTIP and TRING DS2148GN Single -40C to +85 C 49 CSBGA 50mA (RMS) Current Limiter DS2148G Single 0C to +70 C 49 CSBGA DS2148G+ Single 49 CSBGA 0C to +70 C DS21Q48N Four -40C to +85 C 144 CSBGA DS21Q48 Four 0C to +70 C 144 CSBGA + Denotes lead-free/RoHS-compliant package. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 73 REV: 011206 DS2148/DS21Q48 TABLE OF CONTENTS 1 DETAILED DESCRIPTION.................................................................................................. 5 1.1 FUNCTION DESCRIPTION..................................................................................................................5 1.2 DOCUMENT REVISION HISTORY .......................................................................................................6 2 PIN DESCRIPTION............................................................................................................ 10 3 HARDWARE MODE .......................................................................................................... 23 3.1 REGISTER MAP .............................................................................................................................23 3.2 PARALLEL PORT OPERATION .........................................................................................................24 3.3 SERIAL PORT OPERATION..............................................................................................................24 4 CONTROL REGISTERS.................................................................................................... 28 4.1 DEVICE POWER-UP AND RESET.....................................................................................................31 5 STATUS REGISTERS ....................................................................................................... 34 6 DIAGNOSTICS .................................................................................................................. 39 6.1 IN-BAND LOOP CODE GENERATION AND DETECTION ......................................................................39 6.2 LOOPBACKS ..................................................................................................................................43 6.2.1 Remote Loopback (RLB) ......................................................................................................43 6.2.2 Local Loopback (LLB) ...........................................................................................................43 6.2.3 Analog Loopback (ALB) ........................................................................................................44 6.2.4 Dual Loopback (DLB)............................................................................................................44 6.3 PRBS GENERATION AND DETECTION ............................................................................................44 6.4 ERROR COUNTER..........................................................................................................................44 6.4.1 Error Counter Update............................................................................................................45 6.5 ERROR INSERTION ........................................................................................................................45 7 ANALOG INTERFACE ...................................................................................................... 46 7.1 RECEIVER .....................................................................................................................................46 7.2 TRANSMITTER ...............................................................................................................................47 7.3 JITTER ATTENUATOR .....................................................................................................................47 7.4 G.703 SYNCHRONIZATION SIGNAL.................................................................................................48 8 DS21Q48 QUAD LIU ......................................................................................................... 55 9 DC CHARACTERISTICS................................................................................................... 59 9.1 THERMAL CHARACTERISTICS ................................................................................................60 10 AC CHARACTERISTICS................................................................................................... 61 11 PACKAGE INFORMATION ............................................................................................... 70 11.1 44-PIN TQFP (56-G4012-001) .....................................................................................................70 11.2 49-BALL CSGBA (7MM X 7MM) (56-G6006-001)...........................................................................71 11.3 144-BALL CSBGA (17MM X 17MM) (56-G6011-001).....................................................................72 2 of 73