100 DS2154 Enhanced E1 Single-Chip Transceiver www.maxim-ic.com FEATURES PIN CONFIGURATION Complete E1 (CEPT) PCM-30/ISDN-PRI TOP VIEW Transceiver Functionality On-Board Long- and Short-Haul Line Interface for Clock/Data Recovery and Waveshaping DS2154 32-Bit or 128-Bit Crystal-Less Jitter Attenuator Generates Line Build-Outs for Both 120 and 75 Lines Frames to FAS, CAS, and CRC4 Formats Dual On-Board Two-Frame Elastic Store Slip Buffers That can Connect to Asynchronous Backplanes Up to 8.192MHz 8-Bit Parallel Control Port That can be Used Directly on Either Multiplexed or Nonmultiplexed Buses (Intel or Motorola) Extracts and Inserts CAS Signaling Detects and Generates Remote and AIS 1 Alarms LQFP Programmable Output Clocks for Fractional (14mm x 14mm) E1, H0, and H12 Applications Fully Independent Transmit and Receive Functionality ORDERING INFORMATION Full Access to Both Si and Sa Bits Aligned TEMP PIN- PART RANGE PACKAGE with CRC Multiframe DS2154L 0 C to +70 C 100 LQFP Four Separate Loopbacks for Testing DS2154L+ 100 LQFP 0 C to +70 C Functions DS2154LN 100 LQFP -40 C to +85C Large Counters for Bipolar and Code DS2154LN+ 100 LQFP -40 C to +85C Violations, CRC4 Codeword Errors, FAS Errors, and E Bits +Denotes lead-free/RoHS-compliant package. Pin Compatible with DS2152 T1 Enhanced Single-Chip Transceiver 5V Supply Low-Power CMOS 2 100-Pin, 14mm LQFP Package Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 87 REV: 011706 DS2154 TABLE OF CONTENTS 1 DETAILED DESCRIPTION....................................................................................................6 1.1 INTRODUCTION .............................................................................................................................6 1.1.1 New Features......................................................................................................................................... 6 1.2 FUNCTIONAL DESCRIPTION ...........................................................................................................7 1.3 READERS NOTE...........................................................................................................................7 2 PIN DESCRIPTION................................................................................................................9 2.1 TRANSMIT SIDE DIGITAL PINS......................................................................................................11 2.2 RECEIVE SIDE DIGITAL PINS........................................................................................................12 2.3 PARALLEL CONTROL PORT PINS .................................................................................................13 2.4 LINE INTERFACE PINS .................................................................................................................14 2.5 SUPPLY PINS..............................................................................................................................14 3 PARALLEL PORT...............................................................................................................20 4 CONTROL, ID, AND TEST REGISTERS ............................................................................20 4.1 FRAMER LOOPBACK....................................................................................................................29 4.2 LOCAL LOOPBACK.......................................................................................................................29 4.3 REMOTE LOOPBACK....................................................................................................................29 4.4 POWER-UP SEQUENCE...............................................................................................................30 4.5 AUTOMATIC ALARM GENERATION................................................................................................30 5 STATUS AND INFORMATION REGISTERS ......................................................................31 5.1 CRC4 SYNC COUNTER...............................................................................................................33 6 ERROR COUNT REGISTERS.............................................................................................39 6.1 BPV OR CODE VIOLATION COUNTER...........................................................................................39 6.2 CRC4 ERROR COUNTER ............................................................................................................40 6.3 E-BIT COUNTER .........................................................................................................................40 6.4 FAS ERROR COUNTER ...............................................................................................................41 7 DS0 MONITORING FUNCTION ..........................................................................................42 8 SIGNALING OPERATION...................................................................................................46 8.1 PROCESSOR-BASED SIGNALING..................................................................................................46 8.2 HARDWARE-BASED SIGNALING ...................................................................................................49 8.2.1 Receive Side........................................................................................................................................ 49 8.2.2 Transmit Side ....................................................................................................................................... 49 9 PER-CHANNEL CODE (IDLE) GENERATION AND LOOPBACK .....................................51 9.1 TRANSMIT SIDE CODE GENERATION............................................................................................51 9.1.1 Simple Idle Code Insertion and Per-Channel Loopback...................................................................... 51 9.1.2 Per-Channel Code Insertion ................................................................................................................ 52 9.2 RECEIVE SIDE CODE GENERATION..............................................................................................53 10 CLOCK BLOCKING REGISTERS..................................................................................55 11 ELASTIC STORES OPERATION...................................................................................57 11.1 RECEIVE SIDE ............................................................................................................................57 11.2 TRANSMIT SIDE ..........................................................................................................................57 12 ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION................................58 12.1 HARDWARE SCHEME ..................................................................................................................58 12.2 INTERNAL REGISTER SCHEME BASED ON DOUBLE-FRAME ...........................................................58 12.3 INTERNAL REGISTER SCHEME BASED ON CRC4 MULTIFRAME .....................................................61 2 of 87