DS2155LNC2+ Analog Devices

DS2155 T1/E1/J1 Single-Chip Transceiver www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS2155 is a software-selectable T1, E1, or J1 Complete T1/DS1/ISDN-PRI/J1 Transceiver single-chip transceiver (SCT) for short-haul and Functionality long-haul applications. The DS2155 is composed of a Complete E1 (CEPT) PCM-30/ISDN-PRI line interface unit (LIU), framer, HDLC controllers, Transceiver Functionality and a TDM backplane interface, and is controlled by Long-Haul and Short-Haul Line Interface for an 8-bit parallel port configured for Intel or Motorola Clock/Data Recovery and Waveshaping bus operations. The DS2155 is pin and software CMI Coder/Decoder for Optical I/F compatible with the DS2156. Crystal-Less Jitter Attenuator Fully Independent Transmit and Receive The LIU is composed of transmit and receive Functionality interfaces and a jitter attenuator. The transmit Dual HDLC Controllers interface is responsible for generating the necessary Programmable BERT Generator and Detector waveshapes for driving the network and providing Internal Software-Selectable Receive and the correct source impedance depending on the type Transmit-Side Termination Resistors for of media used. T1 waveform generation includes 75 /100 /120 T1 and E1 Interfaces DSX-1 line buildouts as well as CSU line buildouts Dual Two-Frame Elastic-Store Slip Buffers that of -7.5dB, -15dB, and -22.5dB. E1 waveform Connect to Asynchronous Backplanes Up to generation includes G.703 waveshapes for both 75 16.384MHz coax and 120 twisted cables. The receive interface 16.384MHz, 8.192MHz, 4.096MHz, or provides network termination and recovers clock and 2.048MHz Clock Output Synthesized to data from the network. Recovered Network Clock Features continued in Section 3. APPLICATIONS T1/E1/J1 Line Cards ORDERING INFORMATION Switches and Routers Add-Drop Multiplexers PART TEMP RANGE PIN-PACKAGE DS2155L 0C to +70C 100 LQFP DS2155L+ 0C to +70C 100 LQFP DS2155LN -40C to +85C 100 LQFP DS2155LN+ -40C to +85C 100 LQFP DS2155 T1/E1/J1 DS2155G 0C to +70C BACKPLANE 100 CSBGA T1/E1/J1 NETWORK SCT DS2155G+ 0C to +70C 100 CSBGA TDM DS2155GN -40C to +85C 100 CSBGA DS2155GN -40C to +85C 100 CSBGA + Denotes a lead-free/RoHS-compliant package. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 238 REV: 080607 DS2155 1. TABLE OF CONTENTS 1. TABLE OF CONTENTS ............................................................................................................................2 1.1 TABLE OF FIGURES ........................................................................................................................................6 1.2 TABLE OF TABLES..........................................................................................................................................7 2. DATA SHEET REVISION HISTORY .....................................................................................................8 3. MAIN FEATURES....................................................................................................................................10 3.1 FUNCTIONAL DESCRIPTION .........................................................................................................................13 3.2 BLOCK DIAGRAM.........................................................................................................................................15 4. PIN FUNCTION DESCRIPTION ...........................................................................................................19 4.1 TRANSMIT SIDE ...........................................................................................................................................19 4.2 RECEIVE SIDE ..............................................................................................................................................21 4.3 PARALLEL CONTROL PORT PINS .................................................................................................................24 4.4 EXTENDED SYSTEM INFORMATION BUS......................................................................................................25 4.5 USER OUTPUT PORT PINS ............................................................................................................................26 4.6 JTAG TEST ACCESS PORT PINS...................................................................................................................27 4.7 LINE INTERFACE PINS..................................................................................................................................28 4.8 SUPPLY PINS ................................................................................................................................................29 4.9 L AND G PACKAGE PINOUT.........................................................................................................................30 4.10 10MM CSBGA PIN CONFIGURATION ......................................................................................................32 5. PARALLEL PORT ...................................................................................................................................33 5.1 REGISTER MAP ............................................................................................................................................33 6. PROGRAMMING MODEL.....................................................................................................................39 6.1 POWER-UP SEQUENCE.................................................................................................................................40 6.1.1 Master Mode Register.........................................................................................................................40 6.2 INTERRUPT HANDLING ................................................................................................................................41 6.3 STATUS REGISTERS......................................................................................................................................41 6.4 INFORMATION REGISTERS ...........................................................................................................................42 6.5 INTERRUPT INFORMATION REGISTERS ........................................................................................................42 7. SPECIAL PER-CHANNEL REGISTER OPERATION.......................................................................43 8. CLOCK MAP ............................................................................................................................................45 9. T1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS............................................46 9.1 T1 CONTROL REGISTERS .............................................................................................................................46 9.2 T1 TRANSMIT TRANSPARENCY ...................................................................................................................51 9.3 AIS-CI AND RAI-CI GENERATION AND DETECTION ..................................................................................51 9.4 T1 RECEIVE-SIDE DIGITAL-MILLIWATT CODE GENERATION.....................................................................52 10. E1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS............................................55 10.1 E1 CONTROL REGISTERS.........................................................................................................................55 10.2 AUTOMATIC ALARM GENERATION .........................................................................................................59 10.3 E1 INFORMATION REGISTERS..................................................................................................................60 11. COMMON CONTROL AND STATUS REGISTERS ..........................................................................62 11.1 T1/E1 STATUS REGISTERS ......................................................................................................................63 2 of 238