DS2156 T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS2156 is a software-selectable T1, E1, or J1 Complete T1/DS1/ISDN-PRI/J1 Transceiver single-chip transceiver (SCT) for short-haul and Functionality long-haul applications. The backplane is user- Complete E1 (CEPT) PCM-30/ISDN-PRI configurable for a TDM or UTOPIA II bus interface. Transceiver Functionality The DS2156 is composed of a line interface unit User-Selectable TDM or UTOPIA II Bus (LIU), framer, HDLC controllers, and a Interface UTOPIA/TDM backplane interface, and is controlled Long-Haul and Short-Haul Line Interface for by an 8-bit parallel port configured for Intel or Clock/Data Recovery and Waveshaping Motorola bus operations. The DS2156 is pin and CMI Coder/Decoder for Optical I/F software compatible with the DS2155. Crystal-Less Jitter Attenuator Fully Independent Transmit and Receive The LIU is composed of transmit and receive Functionality interfaces and a jitter attenuator. The transmit Dual HDLC Controllers interface is responsible for generating the necessary Programmable BERT Generator and Detector waveshapes for driving the network and providing Internal Software-Selectable Receive and the correct source impedance depending on the type Transmit-Side Termination Resistors for of media used. T1 waveform generation includes 75 /100 /120 T1 and E1 Interfaces DSX-1 line buildouts as well as CSU line buildouts Dual Two-Frame Elastic-Store Slip Buffers that of -7.5dB, -15dB, and -22.5dB. E1 waveform Connect to Asynchronous Backplanes Up to generation includes G.703 waveshapes for both 75 16.384MHz coax and 120 twisted cables. The receive interface 16.384MHz, 8.192MHz, 4.096MHz, or provides network termination and recovers clock and 2.048MHz Clock Output Synthesized to data from the network. Recovered Network Clock Features continued in Section 1. APPLICATIONS Inverse Mux ATM (IMA) ORDERING INFORMATION T1/E1/J1 Line Cards Switches and Routers PART TEMP RANGE PIN-PACKAGE Add-Drop Multiplexers DS2156L 0C to +70C 100 LQFP DS2156L+ 0C to +70C 100 LQFP DS2156LN -40C to +85C 100 LQFP DS2156LN+ -40C to +85C 100 LQFP UTOPIA DS2156G 0C to +70C 100 CSBGA DS2156 DS2156G+ 0C to +70C 100 CSBGA T1/E1/J1 T1/E1/J1 BACKPLANE DS2156GN -40C to +85C 100 CSBGA NETWORK TDM/UTOPIA DS2156GN+ -40C to +85C 100 CSBGA TDM +Denotes lead-free/RoHS-compliant package. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 265 REV: 011606 DS2156 TABLE OF CONTENTS 1. MAIN FEATURES............................................................................................................ 9 2. DETAILED DESCRIPTION............................................................................................ 12 2.1 BLOCK DIAGRAM........................................................................................................................ 14 3. PIN FUNCTION DESCRIPTION .................................................................................... 20 3.1 TDM BACKPLANE ...................................................................................................................... 20 3.1.1 Transmit Side .......................................................................................................................................20 3.1.2 Receive Side........................................................................................................................................23 3.2 UTOPIA BUS ............................................................................................................................ 26 3.2.1 Receive Side........................................................................................................................................26 3.2.2 Transmit Side .......................................................................................................................................27 3.3 PARALLEL CONTROL PORT PINS ................................................................................................ 28 3.4 EXTENDED SYSTEM INFORMATION BUS ...................................................................................... 29 3.5 USER OUTPUT PORT PINS ......................................................................................................... 30 3.6 JTAG TEST ACCESS PORT PINS................................................................................................ 31 3.7 LINE INTERFACE PINS ................................................................................................................ 32 3.8 SUPPLY PINS............................................................................................................................. 33 3.9 L AND G PACKAGE PINOUT ........................................................................................................ 34 3.10 10MM CSBGA PIN CONFIGURATION .......................................................................................... 38 4. PARALLEL PORT ......................................................................................................... 39 4.1 REGISTER MAP.......................................................................................................................... 39 4.2 UTOPIA BUS REGISTERS.......................................................................................................... 45 5. SPECIAL PER-CHANNEL REGISTER OPERATION ................................................... 46 6. PROGRAMMING MODEL ............................................................................................. 48 6.1 POWER-UP SEQUENCE.............................................................................................................. 49 6.1.1 Master Mode Register..........................................................................................................................49 6.2 INTERRUPT HANDLING ............................................................................................................... 50 6.3 STATUS REGISTERS................................................................................................................... 50 6.4 INFORMATION REGISTERS.......................................................................................................... 51 6.5 INTERRUPT INFORMATION REGISTERS ........................................................................................ 51 7. CLOCK MAP.................................................................................................................. 52 8. T1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS ........................... 53 8.1 T1 CONTROL REGISTERS........................................................................................................... 53 8.2 T1 TRANSMIT TRANSPARENCY................................................................................................... 58 8.3 AIS-CI AND RAI-CI GENERATION AND DETECTION ..................................................................... 58 8.4 T1 RECEIVE-SIDE DIGITAL-MILLIWATT CODE GENERATION ......................................................... 59 9. E1 FRAMER/FORMATTER CONTROL AND STATUS REGISTERS........................... 62 9.1 E1 CONTROL REGISTERS .......................................................................................................... 62 9.2 AUTOMATIC ALARM GENERATION............................................................................................... 66 9.3 E1 INFORMATION REGISTERS .................................................................................................... 67 10. COMMON CONTROL AND STATUS REGISTERS ...................................................... 69 10.1 T1/E1 STATUS REGISTERS........................................................................................................ 70 11. I/O PIN CONFIGURATION OPTIONS ........................................................................... 76 12. LOOPBACK CONFIGURATION.................................................................................... 78 12.1 PER-CHANNEL LOOPBACK ......................................................................................................... 80 13. ERROR COUNT REGISTERS....................................................................................... 82 13.1 LINE-CODE VIOLATION COUNT REGISTER (LCVCR) ................................................................... 83 13.1.1 T1 Operation ........................................................................................................................................83 13.1.2 E1 Operation........................................................................................................................................83 13.2 PATH CODE VIOLATION COUNT REGISTER (PCVCR) .................................................................. 85 2 of 265