DS2165Q 16/24/32kbps ADPCM Processor www.maxim-ic.com FEATURES PIN ASSIGNMENT (Top View) Compresses/expands 64kbps PCM voice to/from either 32kbps, 24kbps, or 16kbps Dual fully independent channel architecture device can be programmed to perform either: 4 3 2 1 28 27 26 5 25 NC FSY two expansions 6 24 A0 YOUT 23 7 A1 CS two compressions 8 22 DS2165Q A2 SDI 9 21 A3 SCLK one expansion and one compression 10 20 A4 XOUT Interconnects directly to combo-codec 11 19 A5 NC 12 13 14 15 16 17 18 devices Input to output delay is less than 375 s Simple serial port used to configure the 28-Pin PLCC device On-board time-slot assigner-circuit (TSAC) function allows data to be input/output at various time slots Supports Channel Associated Signaling Each channel can be independently idled or placed into bypass Available hardware mode requires no host processor ideal for voice storage applications Single +5V supply low-power CMOS technology Available in 28-pin PLCC 3V operation version is available (DS2165QL) DESCRIPTION The DS2165Q ADPCM processor chip is a dedicated digital-signal-processing (DSP) chip that has been optimized to perform adaptive-differential pulse-code modulation (ADPCM) speech compression at three different rates. The chip can be programmed to compress (expand) 64kbps voice data down to (up from) either 32kbps, 24kbps, or 16kbps. The compression to 32kbps follows the algorithm specified by CCITT Recommendation G.721 (July 1986) and ANSI document T1.301 (April 1987). The compression to 24kbps follows ANSI document T1.303. The compression to 16kbps follows a proprietary algorithm developed by Dallas Semiconductor. The DS2165Q can switch compression algorithms on-the-fly. This allows the user to make maximum use of the available bandwidth on a dynamic basis. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: DS2165Q OVERVIEW The DS2165Q contains three major functional blocks: a high performance (10 MIPS) DSP engine, two independent PCM interfaces (X and Y) that connect directly to serial time-division-multiplexed (TDM) backplanes, and a serial port that can configure the device on-the-fly by an external controller. A 10MHz master clock is required by the DSP engine. The DS2165Q can be configured to perform either two expansions, two compressions, or one expansion and one compression. The PCM/ADPCM data interfaces support data rates from 256kHz to 4.096MHz. Typically, the PCM data rates are 1.544MHz for -law and 2.048MHz for A-law. Each channel on the device samples the serial input PCM or ADPCM bit stream during a user-programmed input time slot, processes the data and outputs the result during a user- programmed output time slot. Each PCM interface has a control register that specifies functional characteristics (compress, expand, bypass, and idle), data format ( -law or A-law), and algorithm reset control. With the SPS pin strapped high, the software mode is enabled and the serial port can be used to configure the device. In this mode, a novel addressing scheme allows multiple devices to share a common 3-wire control bus, simplifying system-level interconnect. With SPS low, the hardware mode is enabled. This mode disables the serial port and maps certain control register bits to some of the address and serial port pins. Under the hardware mode, no external host controller is required and all PCM/ADPCM input and output time slots default to time slot 0. HARDWARE RESET RST allows the user to reset both channel algorithms and the contents of the internal registers. This pin must be held low for at least 1ms on system power-up after the master clock is stable to ensure that the device has initialized properly. RST should also be asserted when changing to or from the hardware mode. RST clears all bits of the control register for both channels except the IPD bits the IPD bits for both channels are set to 1. SOFTWARE MODE Connecting SPS high enables the software mode. In this mode, an external host controller writes configuration data to the DS2165Q by the serial port through inputs SCLK, SDI, and CS (Figure 2). Each write to the DS2165Q is either a 2-byte write or a 4-byte write. A 2-byte write consists of the address/command byte (ACB), followed by a byte to configure the control register (CR) for either the X or Y channel. The 4-byte write consists of the ACB, followed by a byte to configure the CR, and then 1 byte to set the input time slot and another byte to set the output time slot. ADDRESS/COMMAND BYTE In the software mode, the address/command byte is the first byte written to the serial port it identifies which of the 64 possible ADPCM processors sharing the port wiring is to be updated. Address data must match that at inputs A0 to A5. If no match occurs, the device ignores the following configuration data. If an address match occurs, the next 3 bytes written are accepted as control, input and output time slot data. Bit ACB.6 determines which side (X or Y) of the device is to be updated. The PCM and ADPCM outputs are tri-stated during register updates. 2 of 17