DS2174QN+ Analog Devices

DS2174 EBERT www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS2174 enhanced bit error-rate tester Generates and detects digital patterns for (EBERT) is a software-programmable test-pattern analyzing and trouble-shooting digital generator, receiver, and analyzer capable of communications systems meeting the most stringent error-performance Programmable polynomial length and requirements of digital transmission facilities. It feedback taps for generation of any 32 features bit-serial, nibble-parallel, and byte- pseudorandom patterns up to 2 - 1 up to parallel data interfaces, and generates and 32 taps can be used in the feedback path uniquely synchronizes to pseudorandom patterns Programmable, user-defined pattern n of the form 2 - 1, where n can take on values from registers for long repetitive patterns up to 1 to 32, and user-defined repetitive patterns of any 512 bytes in length length up to 512 octets. Large 48-bit count and bit error count registers APPLICATIONS Software-programmable bit error insertion Routers Fully independent transmit and receive Channel Service Units (CSUs) paths Data Service Units (DSUs) 8-bit parallel-control port Muxes Detects polynomial test patterns in the -2 Switches presence of bit error rates up to 10 Digital-to-Analog Converters (DACs) Programmable for serial, 4-bit parallel, or CPE Equipment 8-bit parallel data interfaces Bridges Serial mode clock rate is 155MHz byte Smart Jack mode is 80MHz for a net 622Mbps OC-3 Available in 44-pin PLCC PIN CONFIGURATION ORDERING INFORMATION TOP VIEW TEMP PIN- PART RANGE PACKAGE DS2174Q 0C to +70C 44 PLCC RDAT3 7 39 D2 DS2174QN -40C to +85C 44 PLCC RDAT4 8 38 D1 RDAT5 9 37 D0 RDAT6 10 36 TDAT7 RDAT7 11 35 TDAT6 GND 12 34 GND DS2174 A0 13 33 TDAT5 A1 14 32 TDAT4 A2 15 31 TDAT3 A3 16 30 TDAT2 CS 17 29 GND Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 24 091302 RD 18 6 RDAT2 WR 19 5 RDAT1 TEST 20 4 RDAT0 TEST 21 3 RCLK EN GND 22 2 RCLK VDD 23 1 VDD TCLK 24 44 D7 TCLK EN 25 43 D6 TCLKO 26 42 D5 TDAT0 27 41 D4 TDAT1 28 40 D3DS2174 . TABLE OF CONTENTS 1. GENERAL OPERATION ................................................................................................................4 1.1 PATTERN GENERATION......................................................................................................................4 1.1.1 Polynomial Generation.......................................................................................... 4 1.1.2 Repetitive Pattern Generation ............................................................................... 4 1.2 PATTERN SYNCHRONIZATION............................................................................................................5 1.2.1 Synchronization...................................................................................................... 5 1.2.2 Polynomial Synchronization .................................................................................. 5 1.2.3 Repetitive Pattern Synchronization ....................................................................... 5 1.3 BIT ERROR RATE (BER) CALCULATION............................................................................................5 1.3.1 Counters................................................................................................................. 5 1.4 GENERATING ERRORS .......................................................................................................................5 1.5 CLOCK DISCUSSION...........................................................................................................................6 1.6 POWER-UP SEQUENCE.......................................................................................................................6 1.7 DETAILED PIN DESCRIPTION .............................................................................................................8 2. PARALLEL CONTROL INTERFACE........................................................................................10 3. CONTROL REGISTERS ...............................................................................................................11 3.1 MODE SELECT .................................................................................................................................13 3.1.1 Error Insertion .....................................................................................................13 3.2 STATUS REGISTER ...........................................................................................................................15 3.3 PSEUDORANDOM PATTERN REGISTERS ...........................................................................................15 3.4 TEST REGISTER................................................................................................................................17 3.5 COUNT REGISTERS ..........................................................................................................................17 4. RAM ACCESS.................................................................................................................................18 4.1 INDIRECT ADDRESSING....................................................................................................................18 5. DC OPERATION ............................................................................................................................19 6. AC TIMING CHARACTERISTICS .............................................................................................20 6.1 PARALLEL PORT ..............................................................................................................................20 6.2 DATA INTERFACE ............................................................................................................................22 7. MECHANICAL DIMENSIONS ....................................................................................................24 2 of 24