DS2180A T1 Transceiver www.dalsemi.com FEATURES PIN ASSIGNMENT Single chip DS1 rate transceiver TMSYNC 1 40 VDD Supports common framing standards TFSYNC 2 39 RLOS 12 frames/superframe 193S TCLK 3 38 RFER 24 frames/superframe 193E TCHCLK 4 37 RBV Three zero suppression modes TSER 5 36 RCL B7 stuffing TMO 6 35 RNEG B8ZS TSIGSEL 7 34 RPOS Transparent TSIGFR 8 33 RST Simple serial interface used for config- TABCD 9 32 TEST uration, control and status monitoring in TLINK 10 31 RSIGSEL processor mode TLCLK 11 30 RSIGFR =Hardware mode requires no host TPOS 12 29 RABCD processor intended for stand-alone app- TNEG 13 28 RMSYNC lications INT 14 27 RFSYNC Selectable 0, 2, 4, 16 state robbed bit SDI 15 26 RSER signaling modes SDO 16 25 RCHCLK Allows mix of clear and non-clear DS0 CS 17 24 RCLK channels on same DS1 link SCLK 18 23 RLCLK Alarm generation and detection SPS 19 22 RLINK Receive error detection and counting for VSS 20 21 RYEL transmission performance monitoring 40-Pin DIP (600-mil) 5V supply, low-power CMOS technology Surface-mount package available, designated DS2180AQ Industrial temperature range of -40C to +85C available, designated DS2180AN or DS2180AQN TSER RNEG 7 39 Compatible to DS2186 Transmit Line TMO RPOS 38 8 TSIGSEL Interface, DS2187 Receive Line Interface, RST 9 37 TSIGFR TEST 36 DS2188 Jitter Attenuator, DS2175 T1/CEPT 10 TABCD RSIGSEL 35 11 Elastic Store, DS2290 T1 Isolation Stik, and TLINK RSIGFR 12 34 DS2291 T1 Long Loop Stik TLCLK RABCD 33 13 TPOS RMSYNC 14 32 TNEG 31 RFSYNC 15 INT RSER 16 30 17 29 RCHCLK SDI 1 of 35 112099 SDO NC 19 CS TCHCLK 5 20 SCLK TCLK 4 21 SPS NC 3 22 VSS TFSYNC 2 23 RYEL TMSYNC 1 24 RLINK VDD 44 25 NC RLOS 43 26 RLCLK RFER 42 27 RCLK RBV 41 NC RCL DS1386/DS1386P DESCRIPTION The DS2180A is a monolithic CMOS device designed to implement primary rate (1.544 MHz) T-carrier transmission systems. The 193S framing mode is intended to support existing Ft/Fs applications (12 frames/superframe). The 193E framing mode supports the extended superframe format (24 frames/superframe). Clear channel capability is provided by selection of appropriate zero suppression and signaling modes. Several functional blocks exist in the transceiver. The transmit framer/formatter generates appropriate framing bits, inserts robbed bit signaling, supervises zero suppression, generates alarms, and provides output clocks useful for data conditioning and decoding. The receive synchronizer establishes frame and multi-frame boundaries by identifying frame signaling bits, extracts signaling data, reports alarms and transmission errors, and provides output clocks useful for data conditioning and decoding. The control block is shared between transmit and receive sides. This block determines the frame, zero suppression, alarm and signaling formats. User access to the control block is by one of two modes. In the processor mode, pins 14 through 18 are a micro-processor/ microcontroller-compatible serial port which can be used for device configuration, control and status monitoring. In the hardware mode, no offboard processor is required. Pins 14 through 18 are reconfigured into hard- wired select pins. Features such as selection clear DS0 channels, insertion of idle code and alteration of sync algorithm are unavailable in the hardware mode. DS2180A BLOCK DIAGRAM Figure 1 2 of 35