DS21Q50 Quad E1 Transceiver www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS21Q50 E1 quad transceiver contains all the Four Complete E1 (CEPT) PCM-30/ISDN-PRI necessary functions for connecting to four E1 lines. Transceivers The on-board clock/data recovery circuitry coverts Long-Haul and Short-Haul Line Interfaces the AMI/HDB3 E1 waveforms to an NRZ serial 32-Bit or 128-Bit Crystal-Less Jitter Attenuator stream. The DS21Q50 automatically adjusts to E1 Frames to FAS, CAS, CCS, and CRC4 Formats 22AWG (0.6mm) twisted-pair cables from 0km to 4MHz/8MHz/16MHz Clock Synthesizer over 2km in length. The device can generate the Flexible System Clock with Automatic Source necessary G.703 waveshapes for both 75 coax and Switching on Loss-of-Clock Source 120 twisted-pair cables. The on-board jitter Two-Frame Elastic-Store Slip Buffer on the attenuators (selectable to either 32 bits or 128 bits) Receive Side can be placed in either the transmit or receive data Interleaving PCM Bus Operation Up to paths. The framers locate the frame and multiframe boundaries and monitor the data streams for alarms. 16.384MHz The device contains a set of internal registers, from Configurable Parallel and Serial Port Operation which the user can access and control the operation Detects and Generates Remote and AIS Alarms of the unit by the parallel control port or serial port. Fully Independent Transmit and Receive The device fully meets all the latest E1 specifications Functionality including ITU-T G.703, G.704, G.706, G.823, G.732, Four Separate Loopback Functions and I.431 ETS 300 011, ETS 300 233, and ETS 300 PRBS Generation/Detection/Error Counting 166 as well as CTR12 and CTR4. 3.3V Low-Power CMOS Large Counters for Bipolar and Code Violations, APPLICATIONS CRC4 Codeword Errors, FAS Word Errors, and DSLAMs E Bits Routers Eight Additional User-Configurable Output Pins IMA and WAN Equipment 100-Pin, 14mm x 14mmLQFP Package PIN CONFIGURATION ORDERING INFORMATION TOP VIEW PIN-PACKAGE PART TEMP RANGE 100 LQFP (14mm) DS21Q50L 0C to +70C 100 LQFP (14mm) DS21Q50LN -40C to +85C DS21Q50 100 1 LQFP Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 87 REV: 013004 DS21Q50 TABLE OF CONTENTS 1. INTRODUCTION ...............................................................................................................................6 2. PIN DESCRIPTION............................................................................................................................9 2.1 PIN FUNCTION DESCRIPTION.........................................................................................................15 2.1.1 System (Backplane) Interface Pins .......................................................................................................15 2.1.2 Alternate Jitter Attenuator....................................................................................................................16 2.1.3 Clock Synthesizer..................................................................................................................................16 2.1.4 Parallel Port Control Pins....................................................................................................................16 2.1.5 Serial Port Control Pins .......................................................................................................................17 2.1.6 Line Interface Pins................................................................................................................................18 2.1.7 Supply Pins ...........................................................................................................................................18 3. HOST INTERFACE PORT..............................................................................................................20 3.1 PARALLEL PORT OPERATION........................................................................................................20 3.2 SERIAL PORT OPERATION .............................................................................................................20 3.3 REGISTER MAP .............................................................................................................................23 4. CONTROL, ID, AND TEST REGISTERS.....................................................................................24 4.1 POWER-UP SEQUENCE ..................................................................................................................25 4.2 FRAMER LOOPBACK .....................................................................................................................28 4.3 AUTOMATIC ALARM GENERATION ...............................................................................................29 4.4 REMOTE LOOPBACK .....................................................................................................................30 4.5 LOCAL LOOPBACK........................................................................................................................30 5. STATUS AND INFORMATION REGISTERS .............................................................................32 5.1 CRC4 SYNC COUNTER .................................................................................................................34 6. ERROR COUNT REGISTERS........................................................................................................39 6.1 BPV OR CODE VIOLATION COUNTER ...........................................................................................39 6.2 CRC4 ERROR COUNTER...............................................................................................................40 6.3 E-BIT/PRBS BIT ERROR COUNTER ..............................................................................................40 6.4 FAS ERROR COUNTER..................................................................................................................41 7. DS0 MONITORING FUNCTION ...................................................................................................42 8. PRBS GENERATION AND DETECTION ....................................................................................45 9. SYSTEM CLOCK INTERFACE.....................................................................................................46 10. TRANSMIT CLOCK SOURCE ......................................................................................................47 11. IDLE CODE INSERTION................................................................................................................48 12. PER-CHANNEL LOOPBACK ........................................................................................................49 13. ELASTIC STORE OPERATION....................................................................................................49 14. ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION .....................................50 15. USER-CONFIGURABLE OUTPUTS.............................................................................................53 16. LINE INTERFACE UNIT................................................................................................................56 16.1 RECEIVE CLOCK AND DATA RECOVERY .......................................................................................56 16.2 TERMINATION...............................................................................................................................57 16.3 RECEIVE MONITOR MODE ............................................................................................................57 16.4 TRANSMIT WAVESHAPING AND LINE DRIVING.............................................................................59 16.5 JITTER ATTENUATORS ..................................................................................................................62 2 of 87