DS21Q58 E1 Quad Transceiver www.maxim-ic.com GENERAL DESCRIPTION FEATURES Four Complete E1 (CEPT) PCM-30/ISDN-PRI The DS21Q58 E1 quad transceiver contains all the Transceivers necessary functions for connecting to four E1 lines. Pin Compatible with the DS21Q50 and DS21Q59 The DS21Q58 is a direct replacement for the Short-Haul Line Interfaces DS21Q50, with the addition of signaling access and improved interrupt handling. It is composed of a line 32-Bit or 128-Bit Crystal-Less Jitter Attenuator interface unit (LIU), framer, and a TDM backplane Frames to FAS, CAS, and CRC4 Formats interface, and is controlled through an 8-bit parallel CAS/CCS Signaling Support port configured for Intel or Motorola bus operations or 4MHz/8MHz/16MHz Clock Synthesizer serial port operation. Flexible System Clock with Automatic Source Switching on Loss-of-Clock Source Two-Frame Elastic-Store Slip Buffer on the APPLICATIONS Receive Side DSLAMs Interleaving PCM Bus Operation Up to 16.384MHz Routers Configurable Parallel and Serial Port Operation IMA and WAN Equipment Detects and Generates Remote and AIS Alarms Fully Independent Transmit and Receive Functionality PIN CONFIGURATION Four Separate Loopback Functions TOP VIEW PRBS Generation/Detection/Error Counting 3.3V Low-Power CMOS Large Counters for Bipolar and Code Violations, Dallas Semiconductor CRC4 Codeword Errors, FAS Word Errors, and DS21Q58 E Bits Eight Additional User-Configurable Output Pins 100 100-Pin (14mm x 14mm) LQFP Package 1 LQFP ORDERING INFORMATION PART TEMP RANGE PIN-PACKAGE Go to www.maxim-ic.com/telecom for a complete list of DS21Q58L 0C to +70C 100 LQFP Telecommunications data sheets, evaluation kits, application notes, and software downloads. DS21Q58LN -40C to +85C 100 LQFP Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 74 REV: 012104 DS21Q58 E1 Quad Transceiver TABLE OF CONTENTS 1. ACRONYMS .......................................................................................................................6 2. DETAILED DESCRIPTION.................................................................................................6 3. BLOCK DIAGRAM .............................................................................................................7 4. PIN DESCRIPTION.............................................................................................................8 4.1 PIN FUNCTION DESCRIPTIONS......................................................................................................12 5. FUNCTIONAL DESCRIPTION .........................................................................................13 6. HOST INTERFACE PORT................................................................................................14 6.1 PARALLEL PORT OPERATION .......................................................................................................14 6.2 SERIAL PORT OPERATION............................................................................................................14 7. REGISTER MAP...............................................................................................................16 8. CONTROL, ID, AND TEST REGISTERS .........................................................................17 8.1 POWER-UP SEQUENCE................................................................................................................18 8.2 FRAMER LOOPBACK ....................................................................................................................21 8.3 AUTOMATIC ALARM GENERATION .................................................................................................22 8.4 REMOTE LOOPBACK ....................................................................................................................22 8.5 LOCAL LOOPBACK .......................................................................................................................23 9. STATUS AND INFORMATION REGISTERS ...................................................................27 9.1 INTERRUPT HANDLING .................................................................................................................28 9.2 CRC4 SYNC COUNTER................................................................................................................29 10. ERROR COUNT REGISTERS..........................................................................................34 10.1 BPV OR CV COUNTER .............................................................................................................34 10.2 CRC4 ERROR COUNTER..........................................................................................................34 10.3 E-BIT/PRBS BIT-ERROR COUNTER ..........................................................................................35 10.4 FAS ERROR COUNTER.............................................................................................................35 11. SIGNALING OPERATION................................................................................................36 11.1 RECEIVE SIGNALING.................................................................................................................36 11.2 TRANSMIT SIGNALING...............................................................................................................36 11.3 CAS OPERATION .....................................................................................................................36 12. DS0 MONITORING FUNCTION .......................................................................................37 13. PRBS GENERATION AND DETECTION.........................................................................39 14. SYSTEM CLOCK INTERFACE ........................................................................................40 15. TRANSMIT CLOCK SOURCE..........................................................................................41 16. IDLE CODE INSERTION..................................................................................................41 17. PER-CHANNEL LOOPBACK ..........................................................................................42 18. ELASTIC STORE OPERATION .......................................................................................42 19. ADDITIONAL (Sa) AND INTERNATIONAL (Si) BIT OPERATION..................................43 20. USER-CONFIGURABLE OUTPUTS................................................................................45 2 of 74