19-5071 12/09 DS2502-E48 48-Bit Node Address Chip www.maxim-ic.com FEATURES PIN CONFIGURATION Factory programmed 48-bit node address TO-92 chip with 768 bits user-programmable OTP- EPROM communicates with the economy of one signal plus ground Provides valid MAC-48/EUI-48 Ethernet address Unique, factory lasered and tested 64-bit registration number assures absolute traceability because no two parts are alike Built-in multidrop controller ensures compatibility with other 1-Wire products Device is an add-only memory where additional data can be programmed into EPROM without disturbing existing data BOTTOM VIEW Reduces control, address, data, power and programming signals to a single pin Directly connects to a single port pin of a TSOC PACKAGE microprocessor and communicates at up to 16.3kbps Presence detector acknowledges when reader first applies voltage Low cost TO-92 or TSOC surface mount TOP VIEW packages ORDERING INFORMATION Reads over a wide voltage range of 2.8V to PART TEMP PIN- 6.0V from -40C to +85C programs at RANGE PACKAGE 11.5V to 12.0V from -40C to + 50C DS2502-E48+ -40C to +85C 3 TO-92 DS2502P-E48+ -40C to +85C 6 TSOC DS2502P-E48+T&R -40C to +85C 6 TSOC + Denotes a lead(Pb)-free/RoHS-compliant package. T&R = Tape and reel. 1-Wire is a registered trademark of Maxim Integrated Products, Inc. DESCRIPTION The DS2502-E48 is a variant of the DS2502 1024-bit add-only memory. It differs from the standard DS2502 in its custom ROM family code 89h, and the UniqueWare Identifier 5E7h in place of the upper 12 bits of the standard ROM serialization field. Otherwise, the electrical and logical behavior is identical to that of the DS2502. For technical details please refer to the DS2502 data sheet. Note : Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 4 DS2502-E48 The first 32 bytes of the DS2502-E48s EPROM memory contain a globally unique 48-bit node address and are write-protected. The data structure follows the conventions of UniqueWare devices using Default Data Structure (Figure 1). This format is also known as UDP (universal data packet) and is commonly used in 1-Wire APIs. Therefore, if using one of those APIs one can call a high level function to read and verify the inverted CRC16. The UDP is defined in Application Note 114, 1-Wire File Structure, and the APIs can be found in the 1-Wire Software Development Kits. Figure 1. NODE ADDRESS CHIP DATA STRUCTURE CRC16 COMPANY ID VALUE EXTENSION ID VALUE PROJECT ID (UNUSED) LENGTH MSB LSB MSB LSB MSB LSB MSB LSB 19 BYTES 3 BYTES CONSTANT 4 BYTES CONSTANT 1 BYTE 2 BYTES 3 BYTES SERIALIZATION FFh 006035h 00001129h 0Ah HIGH ADDRESS LOW ADDRESS The data record starts with a length byte (0Ah) and the 4-byte UniqueWare Project ID 00001129h. The next 6 bytes contain the 48-bit node address which consists of an incrementing 24-bit extension identifier and the IEEE-assigned 24-bit company ID value 006035h. An inverted 16-bit CRC ends the data record. The remaining bytes of the 32-byte memory page remain unprogrammed. Neither the 24-bit extension identifier nor the 24-bit company ID are related to the 64-bit ROM registration number. The ROM registration number is used to provide a unique address to access the DS2502-E48 when multidropped on a 1-Wire bus. EXAMPLE Assume that a manufacturers company ID value is 006035h and the 24-bit extension identifier is 67ABCDh. The 48-bit node address value generated from these two numbers is 00603567ABCDh, whose byte and bit representations are illustrated in Figure 2. Figure 2. SAMPLE NODE ADDRESS VALUE MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE 00 60 35 67 AB CD HEX 0000 0000 0110 0000 0011 0101 0110 0111 1010 1011 1100 1101 BINARY MOST SIGNIFICANT BIT LEAST SIGNIFICANT BIT This information is stored in the DS2502-E48 as 48-bit number with the least significant byte at the lower address. Including the length byte and the inverted CRC, the complete set of data is shown in Figure 3. Figure 3. PHYSICAL ADDRESS AND DATA MAPPING INSIDE THE DEVICE ADDRESS 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 DATA 8D DD 00 60 35 67 AB CD 00 00 11 29 0A 2 of 4