X-On Electronics has gained recognition as a prominent supplier of DS26303L-120+ Telecom Interface ICs across the USA, India, Europe, Australia, and various other global locations. DS26303L-120+ Telecom Interface ICs are a product manufactured by Analog Devices. We provide cost-effective solutions for Telecom Interface ICs, ensuring timely deliveries around the world.

DS26303L-120+ Analog Devices

DS26303L-120+ electronic component of Analog Devices
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Part No.DS26303L-120+
Manufacturer: Analog Devices
Category: Telecom Interface ICs
Description: Telecom Interface ICs 3.3V E1/T1/J1 Short Haul Octal LIU
Datasheet: DS26303L-120+ Datasheet (PDF)
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



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MOQ : 1
Multiples : 1
1 : USD 32.467
10 : USD 30.8385
25 : USD 25.6223
50 : USD 25.6223
N/A

Obsolete
   
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We are delighted to provide the DS26303L-120+ from our Telecom Interface ICs category, at competitive rates not only in the United States, Australia, and India, but also across Europe and beyond. A long established and extensive electronic component distribution network has enhanced our global reach and dependability, ensuring cost savings through prompt deliveries worldwide. Client satisfaction is at the heart of our business, where every component counts and every customer matters. Our technical service team is ready to assist you. From product selection to after-sales support, we strive to deliver a seamless and satisfying experience. Are you ready to experience the best in electronic component distribution? Contact X-ON Electronics today and discover why X-On are a preferred choice for the DS26303L-120+ and other electronic components in the Telecom Interface ICs category and beyond.

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DS26303 3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit www.maxim-ic.com GENERAL DESCRIPTION FEATURES 8 Complete E1, T1, or J1 Short-Haul Line The DS26303 is an 8-channel short-haul line Interface Units interface unit (LIU) that supports E1/T1/J1 from a single 3.3V power supply. A wide variety of Independent E1, T1, or J1 Selections applications are supported through internal Internal Software-Selectable Transmit and termination or external termination. A single bill of Receive-Side Termination material can support E1/T1/J1 with minimum external Crystal-Less Jitter Attenuator components. Redundancy is supported through nonintrusive monitoring, optimal high-impedance Selectable Single-Rail and Dual-Rail Mode modes, and configurable 1:1 or 1+1 backup and AMI or HDB3/B8ZS Line Encoding and enhancements. An on-chip synthesizer generates the Decoding E1/T1/J1 clock rates by a single master clock input of Detection and Generation of AIS various frequencies. Two clock output references are Digital/Analog Loss-of-Signal Detection as also offered. per T1.231, G.775, and ETS 300 233 External Master Clock can be Multiple of APPLICATIONS 2.048MHz or 1.544MHz for T1/J1 or E1 T1 Digital Cross-Connects Operation This Clock will be Internally ATM and Frame Relay Equipment Adapted for T1 or E1 Use Wireless Base Stations Built-In BERT Tester for Diagnostics ISDN Primary Rate Interface E1/T1/J1 Multiplexer and Channel Banks 8-Bit Parallel Interface Support for Intel or E1/T1/J1 LAN/WAN Routers Motorola Mode or a 4-Wire Serial Interface Hardware Mode Interface Support FUNCTIONAL DIAGRAM Transmit Short-Circuit Protection G.772 Nonintrusive Monitoring Software Control, Jtag MODESEL Hardware Control Specification Compliance to the Latest T1 and JTAG and E1 StandardsANSI T1.102, AT&T Pub RLOS 62411, T1.231, T1.403, ITU-T G.703, G.742, G.775, G.823, ETS 300 166, and ETS 300 233 RTIP RPOS Single 3.3V Supply with 5V Tolerant I/O Receiver RNEG RRING RCLK JTAG Boundary Scan as per IEEE 1149.1 TPOS TTTIP Transmitter TNEG 144-Pin eLQFP Package TRING TCLK 1 ORDERING INFORMATION PART TEMP RANGE PIN-PACKAGE 8 DS26303L-XXX 0C to +70C 144 eLQFP DS26303L-XXX+ 0C to +70C 144 eLQFP DS26303 DS26303LN-XXX -40C to +85C 144 eLQFP DS26303LN-XXX+ -40C to +85C 144 eLQFP Note: When XXX is 075, the part defaults to 75 impedance in E1 mode when XXX is 120, the part defaults to 120 impedance. + Denotes a lead-free/RoHS-compliant package. e = Exposed Pad. Note : Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device m ay be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 101 REV: 053107 DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit TABLE OF CONTENTS 1 DETAILED DESCRIPTION ...............................................................................................................6 2 TELECOM SPECIFICATIONS COMPLIANCE.................................................................................7 3 BLOCK DIAGRAMS .........................................................................................................................9 4 PIN DESCRIPTION .........................................................................................................................11 4.1 HARDWARE AND HOST PORT OPERATION ......................................................................................20 4.1.1 Hardware Mode................................................................................................................................... 20 4.1.2 Serial Port Operation .......................................................................................................................... 21 4.1.3 Parallel Port Operation........................................................................................................................ 22 4.1.4 Interrupt Handling ............................................................................................................................... 22 5 REGISTERS....................................................................................................................................24 5.1 REGISTER DESCRIPTION ...............................................................................................................29 5.1.1 Primary Registers................................................................................................................................ 29 5.1.2 Secondary Registers........................................................................................................................... 38 5.1.3 Individual LIU Registers ...................................................................................................................... 40 5.1.4 BERT Registers .................................................................................................................................. 47 6 FUNCTIONAL DESCRIPTION........................................................................................................54 6.1 POWER-UP AND RESET.................................................................................................................54 6.2 MASTER CLOCK ............................................................................................................................54 6.3 TRANSMITTER ...............................................................................................................................55 6.3.1 Transmit Line Templates .................................................................................................................... 56 6.3.2 LIU Transmit Front-End ...................................................................................................................... 58 6.3.3 Dual-Rail Mode ................................................................................................................................... 59 6.3.4 Single-Rail Mode................................................................................................................................. 59 6.3.5 Zero SuppressionB8ZS or HDB3 .................................................................................................... 59 6.3.6 Transmit Power-Down ........................................................................................................................ 59 6.3.7 Transmit All Ones................................................................................................................................ 59 6.3.8 Driver Fail Monitor............................................................................................................................... 59 6.4 RECEIVER.....................................................................................................................................59 6.4.1 Peak Detector and Slicer .................................................................................................................... 59 6.4.2 Clock and Data Recovery ................................................................................................................... 59 6.4.3 Loss of Signal...................................................................................................................................... 60 6.4.4 AIS ...................................................................................................................................................... 60 6.4.5 Bipolar Violation and Excessive Zero Detector................................................................................... 62 6.4.6 LIU Receiver Front-End ...................................................................................................................... 62 6.5 HITLESS-PROTECTION SWITCHING (HPS) ......................................................................................62 6.6 JITTER ATTENUATOR.....................................................................................................................64 6.7 G.772 MONITOR ...........................................................................................................................65 6.8 LOOPBACKS..................................................................................................................................65 6.8.1 Analog Loopback ................................................................................................................................ 65 6.8.2 Digital Loopback.................................................................................................................................. 65 6.8.3 Remote Loopback............................................................................................................................... 66 6.8.4 Dual Loopback .................................................................................................................................... 67 6.9 BERT...........................................................................................................................................68 6.9.1 Configuration and Monitoring.............................................................................................................. 68 6.9.2 BERT Interrupt Handling..................................................................................................................... 69 6.9.3 Receive Pattern Detection .................................................................................................................. 69 6.9.4 Transmit Pattern Generation............................................................................................................... 71 7 JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT...................................72 7.1 TAP CONTROLLER STATE MACHINE ..............................................................................................73 7.1.1 Test-Logic-Reset................................................................................................................................. 73 7.1.2 Run-Test-Idle ...................................................................................................................................... 73 7.1.3 Select-DR-Scan .................................................................................................................................. 73 7.1.4 Capture-DR......................................................................................................................................... 73 2 of 101

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Electronic integrated circuits- Processors and controllers, whether or not combined with memories, converters, logic circuits, amplifiers, clock and timing circuits, or other circuits
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