DS26324GN+ Analog Devices

DEMO KIT AVAILABLE 19-5754 Rev 3/11 DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit GENERAL DESCRIPTION FEATURES 16 E1, T1, or J1 Short-Haul Line Interface The DS26324 is a 16-channel short-haul line Units interface unit (LIU) that supports E1/T1/J1 from a single 3.3V power supply. A wide variety of Independent E1, T1 or J1 Selections applications are supported through internal Fully Internal Impedance Match Requires No impedance matching. A single bill of material can External Resistors support E1/T1/J1 that requires no external Software-Selectable Transmit and Receive- termination. Redundancy is supported through Side Impedance Match nonintrusive monitoring, optimal high-impedance modes and configurable 1:1 or 1+1 backup Crystal-Less Jitter Attenuator enhancements. An on-chip synthesizer generates the Selectable Single-Rail and Dual-Rail Mode E1/T1/J1 clock rates by a single master clock input of and AMI or HDB3/B8ZS Line Encoding and various frequencies. Two clock output references are Decoding also offered. The device is offered in a 256-pin Detection and Generation of AIS TE-CSBGA, the smallest package available for a Digital/Analog Loss of Signal Detection as 16-channel LIU. per T1.231, G.775 and ETS 300 233 APPLICATIONS External Master Clock Can Be Multiple of 2.048MHz or 1.544MHz for T1/J1 or E1 T1 Digital Cross-Connects Operation This Clock Will Be Internally ATM and Frame Relay Equipment Adapted for T1 or E1 Usage Wireless Base Stations ISDN Primary Rate Interface Receiver Signal Level Indicator from -2.5dB to E1/T1/J1 Multiplexer and Channel Banks -20dB in 2.5dB Increments E1/T1/J1 LAN/WAN Routers Two Built-In BERT Testers for Diagnostics FUNCTIONAL DIAGRAM 8-Bit Parallel Interface Support for Intel or Motorola Mode or a 4-Wire Serial Interface JTAG Transmit Short-Circuit Protection SOFTWARE CONTROL G.772 Nonintrusive Monitoring AND JTAG Receive Monitor Mode Handles Combinations LOSS of 14dB to 20dB of Resistive Attenuation Along with 12dB to 30dB of Cable Attenuation RTIP RPOS Specification Compliance to the Latest T1 RECEIVER RNEG RRING RCLK and E1 Standards TPOS TTIP Single 3.3V Supply with 5V Tolerant I/O TNEG TRANSMITTER TCLK TRING JTAG Boundary Scan as Per IEEE 1149.1 1 ORDERING INFORMATION PART TEMP RANGE PIN-PACKAGE DS26324G+ 0C to +70C 256 TE-CSBGA 16 DS26324GN+ -40C to +85C 256 TE-CSBGA DS26324G 0C to +70C 256 TE-CSBGA DS26324GN -40C to +85C 256 TE-CSBGA +Denotes a lead(Pb)-free/RoHS compliant package. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 120 DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit TABLE OF CONTENTS 1 STANDARDS COMPLIANCE ........................................................................................................ 6 1.1 TELECOM SPECIFICATIONS COMPLIANCE ....................................................................................... 6 2 DETAILED DESCRIPTION ............................................................................................................ 7 3 BLOCK DIAGRAMS ...................................................................................................................... 8 4 PIN DESCRIPTION ...................................................................................................................... 10 5 FUNCTIONAL DESCRIPTION ..................................................................................................... 17 5.1 PORT OPERATION ...................................................................................................................... 17 5.1.1 Serial Port Operation ..................................................................................................................... 17 5.1.2 Parallel Port Operation ................................................................................................................... 18 5.1.3 Interrupt Handling .......................................................................................................................... 18 5.2 POWER-UP AND RESET .............................................................................................................. 19 5.3 MASTER CLOCK ......................................................................................................................... 19 5.4 TRANSMITTER ............................................................................................................................ 20 5.4.1 Transmit Line Templates ................................................................................................................ 22 5.4.2 LIU Transmit Front-End .................................................................................................................. 25 5.4.3 Transmit Dual-Rail Mode ............................................................................................................... 26 5.4.4 Transmit Single-Rail Mode ............................................................................................................. 26 5.4.5 Zero SuppressionB8ZS or HDB3 ................................................................................................ 26 5.4.6 Transmit Power-Down.................................................................................................................... 26 5.4.7 Transmit All Ones .......................................................................................................................... 27 5.4.8 Driver Fail Monitor.......................................................................................................................... 27 5.5 RECEIVER .................................................................................................................................. 27 5.5.1 Receiver Impedance Matching Calibration ..................................................................................... 27 5.5.2 Receiver Monitor Mode .................................................................................................................. 27 5.5.3 Peak Detector and Slicer ............................................................................................................... 28 5.5.4 Receive Level Indicator .................................................................................................................. 28 5.5.5 Clock and Data Recovery............................................................................................................... 28 5.5.6 Loss of Signal ................................................................................................................................ 28 5.5.7 AIS ................................................................................................................................................ 29 5.5.8 Receive Dual-Rail Mode ................................................................................................................ 29 5.5.9 Receive Single-Rail Mode .............................................................................................................. 30 5.5.10 Bipolar Violation and Excessive Zero Detector ............................................................................... 30 5.6 JITTER ATTENUATOR .................................................................................................................. 31 5.7 G.772 MONITOR ........................................................................................................................ 32 5.8 LOOPBACKS ............................................................................................................................... 32 5.8.1 Analog Loopback ........................................................................................................................... 32 5.8.2 Digital Loopback ............................................................................................................................ 33 5.8.3 Remote Loopback .......................................................................................................................... 33 5.9 BERT........................................................................................................................................ 34 5.9.1 General Description ....................................................................................................................... 34 5.9.2 Configuration and Monitoring ......................................................................................................... 35 5.9.3 Receive Pattern Detection.............................................................................................................. 36 5.9.4 Transmit Pattern Generation .......................................................................................................... 38 6 REGISTER MAPS AND DEFINITION .......................................................................................... 39 6.1 REGISTER DESCRIPTION ............................................................................................................. 48 6.1.1 Primary Register Bank ................................................................................................................... 48 6.1.2 Secondary Register Bank............................................................................................................... 63 6.1.3 Individual LIU Register Bank .......................................................................................................... 66 6.1.4 BERT Registers ............................................................................................................................. 84 7 JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT .................................. 91 7.1 TAP CONTROLLER STATE MACHINE ............................................................................................ 92 7.1.1 Test-Logic-Reset ........................................................................................................................... 92 7.1.2 Run-Test-Idle ................................................................................................................................. 92 2 of 120