DS26334GN+ Analog Devices

19-5753 Rev 3/11 DEMO KIT AVAILABLE DS26334 3.3V, 16-Channel, E1/T1/J1 Short- and Long-Haul Line Interface Unit GENERAL DESCRIPTION FEATURES 16 E1, T1, or J1 Short/Long-Haul Line The DS26334 is a 16-channel short/long-haul line Interface Units interface unit (LIU) that supports E1/T1/J1 from a single 3.3V power supply. A single bill of material can Independent E1, T1 or J1 Selections support E1/T1/J1 that requires no external Fully Internal Impedance Match Requires No termination. Redundancy is supported through External Resistors nonintrusive monitoring, optimal high-impedance Software-Selectable Transmit and Receive- modes and configurable 1:1 or 1+1 backup Side Impedance Match enhancements. An on-chip synthesizer generates the E1/T1/J1 clock rates by a single master clock input of Crystal-Less Jitter Attenuator various frequencies. Two clock output references are Selectable Single-Rail and Dual-Rail Mode also offered. The device is offered in a 256-pin and AMI or HDB3/B8ZS Line Encoding and TE-CSBGA, the smallest package available for a Decoding 16-channel LIU. Detection and Generation of AIS Digital/Analog Loss of Signal Detection as APPLICATIONS per T1.231, G.775 and ETS 300 233 T1 Digital Cross-Connects External Master Clock Can Be Multiple of ATM and Frame Relay Equipment 2.048MHz or 1.544MHz for T1/J1 or E1 Wireless Base Stations Operation This Clock Will Be Internally ISDN Primary Rate Interface Adapted for T1 or E1 Usage E1/T1/J1 Multiplexer and Channel Banks E1/T1/J1 LAN/WAN Routers Receiver Signal Level Indicator from -2.5dB to -38dB in T1 Mode and -3dB to -43dB in E1 FUNCTIONAL DIAGRAM Mode in 2.5dB Increments Two Built-In BERT Testers for Diagnostics JTAG MODE 8-Bit Parallel Interface Support for Intel or SOFTWARE CONTROL AND JTAG Motorola Mode or a 4-Wire Serial Interface Transmit Short-Circuit Protection LOSS G.772 Nonintrusive Monitoring Receive Monitor Mode Handles Combinations RTIP RPOS RECEIVER RNEG of 14dB to 30dB of Resistive Attenuation RRING RCLK Along with 12dB to 30dB of Cable Attenuation TPOS TTIP TNEG TRANSMITTER TCLK TRING Specification Compliance to the Latest T1 and E1 Standards 1 Single 3.3V Supply with 5V Tolerant I/O JTAG Boundary Scan as Per IEEE 1149.1 ORDERING INFORMATION 16 PART TEMP RANGE PIN-PACKAGE DS26334G 0C to +70C 256 TE-CSBGA DS26334G+ 0C to +70C 256 TE-CSBGA DS26334GN -40C to +85C 256 TE-CSBGA DS26334GN+ -40C to +85C 256 TE-CSBGA +Denotes a lead(Pb)-free/RoHS compliant package. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 121 DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit TABLE OF CONTENTS 1 STANDARDS COMPLIANCE ........................................................................................................ 6 1.1 TELECOM SPECIFICATIONS COMPLIANCE ....................................................................................... 6 2 DETAILED DESCRIPTION ............................................................................................................ 7 3 BLOCK DIAGRAMS ...................................................................................................................... 8 4 PIN DESCRIPTION ...................................................................................................................... 10 5 FUNCTIONAL DESCRIPTION ..................................................................................................... 17 5.1 PORT OPERATION ...................................................................................................................... 17 5.1.1 Serial Port Operation ..................................................................................................................... 17 5.1.2 Parallel Port Operation ................................................................................................................... 18 5.1.3 Interrupt Handling .......................................................................................................................... 18 5.2 POWER-UP AND RESET .............................................................................................................. 19 5.3 MASTER CLOCK ......................................................................................................................... 19 5.4 TRANSMITTER ............................................................................................................................ 20 5.4.1 Transmit Line Templates ................................................................................................................ 22 5.4.2 LIU Transmit Front-End .................................................................................................................. 25 5.4.3 Transmit Dual-Rail Mode ............................................................................................................... 26 5.4.4 Transmit Single-Rail Mode ............................................................................................................. 26 5.4.5 Zero SuppressionB8ZS or HDB3 ................................................................................................ 26 5.4.6 Transmit Power-Down.................................................................................................................... 26 5.4.7 Transmit All Ones .......................................................................................................................... 27 5.4.8 Driver Fail Monitor.......................................................................................................................... 27 5.5 RECEIVER .................................................................................................................................. 27 5.5.1 Receiver Impedance Matching Calibration ..................................................................................... 27 5.5.2 Receiver Monitor Mode .................................................................................................................. 27 5.5.3 Peak Detector and Slicer ............................................................................................................... 28 5.5.4 Receive Level Indicator .................................................................................................................. 28 5.5.5 Clock and Data Recovery............................................................................................................... 28 5.5.6 Loss of Signal ................................................................................................................................ 28 5.5.7 AIS ................................................................................................................................................ 29 5.5.8 Receive Dual-Rail Mode ................................................................................................................ 30 5.5.9 Receive Single-Rail Mode .............................................................................................................. 30 5.5.10 Bipolar Violation and Excessive Zero Detector ............................................................................... 30 5.6 JITTER ATTENUATOR .................................................................................................................. 31 5.7 G.772 MONITOR ........................................................................................................................ 32 5.8 LOOPBACKS ............................................................................................................................... 32 5.8.1 Analog Loopback ........................................................................................................................... 32 5.8.2 Digital Loopback ............................................................................................................................ 33 5.8.3 Remote Loopback .......................................................................................................................... 33 5.9 BERT........................................................................................................................................ 34 5.9.1 General Description ....................................................................................................................... 34 5.9.2 Configuration and Monitoring ......................................................................................................... 35 5.9.3 Receive Pattern Detection.............................................................................................................. 36 5.9.4 Transmit Pattern Generation .......................................................................................................... 38 6 REGISTER MAPS AND DEFINITION .......................................................................................... 39 6.1 REGISTER DESCRIPTION ............................................................................................................. 48 6.1.1 Primary Register Bank ................................................................................................................... 48 6.1.2 Secondary Register Bank............................................................................................................... 63 6.1.3 Individual LIU Register Bank .......................................................................................................... 66 6.1.4 BERT Registers ............................................................................................................................. 85 7 JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT .................................. 92 7.1 TAP CONTROLLER STATE MACHINE ............................................................................................ 93 7.1.1 Test-Logic-Reset ........................................................................................................................... 93 7.1.2 Run-Test-Idle ................................................................................................................................. 93 2 of 121