DESIGN KIT AVAILABLE DS26502 T1/E1/J1/64KCC BITS Element www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS26502 is a building-integrated timing- G.703 2048kHz Synchronization Interface supply (BITS) clock-recovery element. It also Compliant functions as a basic T1/E1 transceiver. The G.703 64kHz Centralized (Option A) and receiver portion can recover a clock from T1, Codirectional Timing Interface Compliant E1, 64kHz composite clock (64KCC), and G.703 Appendix II 64kHz and 6312kHz 6312kHz synchronization timing interfaces. In Japanese Synchronization Interface T1 and E1 modes, the Synchronization Status Compliant Message (SSM) can also be recovered. The Interfaces to Standard T1/J1 (1.544MHz) and transmit portion can directly interface to T1, E1, E1 (2.048MHz) or 64KCC synchronization interfaces as well as Interface to CMI-Coded T1/J1 and E1 source the SSM in T1 and E1 modes. The Short- and Long-Haul Line Interface DS26502 can translate between any of the Transmit and Receive T1 and E1 SSM supported inbound synchronization clock rates to Messages with Message Validation any supported outbound rate. A separate output T1/E1 Jitter Attenuator with Bypass Mode is provided to source a 6312kHz clock. The Fully Independent Transmit and Receive device is controlled through a parallel, serial, or Functionality hardware controller port. Internal Software-Selectable Receive- and Transmit-Side Termination for 75/100 /110/120 T1, E1, and Composite Clock Interfaces APPLICATIONS Monitor Mode for Bridging Applications BITS Timing Accepts 16.384MHz, 12.8MHz, 8.192MHz, Rate Conversion 4.096MHz, 2.048MHz, or 1.544MHz Master Clock 64kHz, 8kHz, and 400Hz Outputs in ORDERING INFORMATION Composite Clock Mode PART TEMP RANGE PIN-PACKAGE 8-Bit Parallel Control Port, Multiplexed or DS26502L 0C to +70C 64 LQFP Nonmultiplexed, Intel or Motorola Serial (SPI) Control Port DS26502LN -40C to +85C 64 LQFP Hardware Contr-ol Mode Provides LOS, AIS, and LOF Indications Through Hardware Output Pins Fast Transmitter-Output Disable Through Device Pin for Protection Switching IEEE 1149.1 JTAG Boundary Scan 3.3V Supply with 5V Tolerant Inputs and Outputs Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 125 REV: 042208 DS26502 T1/E1/J1/64KCC BITS Element TABLE OF CONTENTS 1. FEATURES.......................................................................................................................7 1.1 GENERAL .....................................................................................................................................7 1.2 LINE INTERFACE ...........................................................................................................................7 1.3 JITTER ATTENUATOR (T1/E1 MODES ONLY) ..................................................................................7 1.4 FRAMER/FORMATTER ...................................................................................................................8 1.5 TEST AND DIAGNOSTICS ...............................................................................................................8 1.6 CONTROL PORT............................................................................................................................8 2. SPECIFICATIONS COMPLIANCE ...................................................................................9 3. BLOCK DIAGRAMS .......................................................................................................11 4. PIN FUNCTION DESCRIPTION .....................................................................................14 4.1 TRANSMIT PLL ...........................................................................................................................14 4.2 TRANSMIT SIDE ..........................................................................................................................14 4.3 RECEIVE SIDE ............................................................................................................................15 4.4 CONTROLLER INTERFACE............................................................................................................16 4.5 JTAG.........................................................................................................................................21 4.6 LINE INTERFACE .........................................................................................................................21 4.7 POWER ......................................................................................................................................22 5. PINOUT...........................................................................................................................23 6. HARDWARE CONTROLLER INTERFACE....................................................................26 6.1 TRANSMIT CLOCK SOURCE .........................................................................................................26 6.2 INTERNAL TERMINATION..............................................................................................................26 6.3 LINE BUILD-OUT .........................................................................................................................27 6.4 RECEIVER OPERATING MODES....................................................................................................27 6.5 TRANSMITTER OPERATING MODES..............................................................................................28 6.6 MCLK PRE-SCALER ...................................................................................................................28 6.7 OTHER HARDWARE CONTROLLER MODE FEATURES ....................................................................29 7. PROCESSOR INTERFACE............................................................................................30 7.1 PARALLEL PORT FUNCTIONAL DESCRIPTION................................................................................30 7.2 SPI SERIAL PORT INTERFACE FUNCTIONAL DESCRIPTION............................................................30 7.2.1 Clock Phase and Polarity..................................................................................................................... 30 7.2.2 Bit Order............................................................................................................................................... 30 7.2.3 Control Byte ......................................................................................................................................... 30 7.2.4 Burst Mode........................................................................................................................................... 30 7.2.5 Register Writes..................................................................................................................................... 31 7.2.6 Register Reads .................................................................................................................................... 31 7.3 REGISTER MAP...........................................................................................................................32 7.3.1 Power-Up Sequence............................................................................................................................ 34 7.3.2 Test Reset Register ............................................................................................................................. 34 7.3.3 Mode Configuration Register ............................................................................................................... 35 7.4 INTERRUPT HANDLING ................................................................................................................38 7.5 STATUS REGISTERS....................................................................................................................38 7.6 INFORMATION REGISTERS...........................................................................................................39 7.7 INTERRUPT INFORMATION REGISTERS .........................................................................................39 8. T1 FRAMER/FORMATTER CONTROL REGISTERS ....................................................40 8.1 T1 CONTROL REGISTERS............................................................................................................40 9. E1 FRAMER/FORMATTER CONTROL REGISTERS....................................................46 9.1 E1 CONTROL REGISTERS ...........................................................................................................46 2 of 125