DESIGN KIT AVAILABLE DS26503 T1/E1/J1 BITS Element www.maxim-ic.com GENERAL DESCRIPTION FEATURES The DS26503 is a building-integrated timing- G.703 2048kHz Synchronization Interface supply (BITS) clock-recovery element. It also Compliant functions as a basic T1/E1 transceiver. The G.703 6312kHz Japanese Synchronization receiver portion can recover a clock from T1, Interface Compliant E1, and 6312kHz synchronization timing Interfaces to Standard T1/J1 (1.544MHz) and interfaces. In T1 and E1 modes, the E1 (2.048MHz) Synchronization Status Message (SSM) can also Interface to CMI-Coded T1/J1 and E1 be recovered. The transmit portion can directly Short- and Long-Haul Line Interface interface to T1 or E1 interfaces as well as source Transmit and Receive T1 and E1 SSM the SSM in T1 and E1 modes. The DS26503 can Messages with Message Validation translate between any of the supported inbound T1/E1 Jitter Attenuator with Bypass Mode synchronization clock rates to any supported Fully Independent Transmit and Receive outbound rate. A separate output is provided to Functionality source a 6312kHz clock. The device is Internal Software-Selectable Receive- and controlled through a parallel, serial, or hardware Transmit-Side Termination for controller port. 75/100 /110/120 Monitor Mode for Bridging Applications Accepts 16.384MHz, 12.8MHz, 8.192MHz, 4.096MHz, 2.048MHz, or 1.544MHz Master APPLICATIONS Clock BITS Timing 8-Bit Parallel Control Port, Multiplexed or Rate Conversion Nonmultiplexed, Intel or Motorola Basic Transceiver Serial (SPI) Control Port Hardware Control Mode Provides LOS, AIS, and LOF Indications ORDERING INFORMATION Through Hardware Output Pins PART TEMP RANGE PIN-PACKAGE Fast Transmitter-Output Disable Through DS26503L 0C to +70C 64 LQFP Device Pin for Protection Switching IEEE 1149.1 JTAG Boundary Scan DS26503LN -40C to +85C 64 LQFP 3.3V Supply with 5V-Tolerant Inputs and Outputs Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 122 REV: 121707 DS26503 T1/E1/J1 BITS Element TABLE OF CONTENTS 1. FEATURES ....................................................................................................................................7 1.1 GENERAL .....................................................................................................................................7 1.2 LINE INTERFACE ...........................................................................................................................7 1.3 JITTER ATTENUATOR (T1/E1 MODES ONLY) ..................................................................................7 1.4 FRAMER/FORMATTER ...................................................................................................................8 1.5 TEST AND DIAGNOSTICS ...............................................................................................................8 1.6 CONTROL PORT............................................................................................................................8 2. SPECIFICATIONS COMPLIANCE.................................................................................................9 3. BLOCK DIAGRAMS.....................................................................................................................11 4. PIN FUNCTION DESCRIPTION...................................................................................................14 4.1 TRANSMIT PLL ...........................................................................................................................14 4.2 TRANSMIT SIDE ..........................................................................................................................14 4.3 RECEIVE SIDE ............................................................................................................................15 4.4 CONTROLLER INTERFACE............................................................................................................16 4.5 JTAG.........................................................................................................................................21 4.6 LINE INTERFACE .........................................................................................................................21 4.7 POWER ......................................................................................................................................22 5. PINOUT ........................................................................................................................................23 6. HARDWARE CONTROLLER INTERFACE.................................................................................26 6.1 TRANSMIT CLOCK SOURCE .........................................................................................................26 6.2 INTERNAL TERMINATION..............................................................................................................26 6.3 LINE BUILD-OUT .........................................................................................................................27 6.4 RECEIVER OPERATING MODES....................................................................................................27 6.5 TRANSMITTER OPERATING MODES..............................................................................................28 6.6 MCLK PRE-SCALER ...................................................................................................................28 6.7 OTHER HARDWARE CONTROLLER MODE FEATURES ....................................................................29 7. PROCESSOR INTERFACE .........................................................................................................30 7.1 PARALLEL PORT FUNCTIONAL DESCRIPTION................................................................................30 7.2 SPI SERIAL PORT INTERFACE FUNCTIONAL DESCRIPTION............................................................30 7.2.1 Clock Phase and Polarity......................................................................................................30 7.2.2 Bit Order................................................................................................................................30 7.2.3 Control Byte ..........................................................................................................................30 7.2.4 Burst Mode............................................................................................................................30 7.2.5 Register Writes .....................................................................................................................31 7.2.6 Register Reads .....................................................................................................................31 7.3 REGISTER MAP...........................................................................................................................32 7.3.1 Power-Up Sequence.............................................................................................................34 7.3.2 Test Reset Register ..............................................................................................................34 7.3.3 Mode Configuration Register ................................................................................................35 7.4 INTERRUPT HANDLING ................................................................................................................38 7.5 STATUS REGISTERS....................................................................................................................38 7.6 INFORMATION REGISTERS...........................................................................................................39 7.7 INTERRUPT INFORMATION REGISTERS .........................................................................................39 8. T1 FRAMER/FORMATTER CONTROL REGISTERS .................................................................40 8.1 T1 CONTROL REGISTERS............................................................................................................40 2 of 122