DESIGN KIT AVAILABLE DS26504 T1/E1/J1/64KCC BITS Element www.maxim-ic.com Transmit and Receive T1 BOC SSM Messages GENERAL DESCRIPTION with Receive Message Change of State and The DS26504 is a building-integrated timing-supply Validation Indication (BITS) clock-recovery element. It also functions as a Transmit and Receive E1 Sa(n) Bit SSM basic T1/E1 transceiver. The receiver portion can Messages with Receive Message Change of State recover a clock from T1, E1, 64kHz composite clock Indication (64KCC), and 6312kHz synchronization timing Crystal-Less Jitter Attenuator with Bypass Mode interfaces. In T1 and E1 modes, the Synchronization for T1 and E1 Operation Status Message (SSM) can also be recovered. The Fully Independent Transmit and Receive transmit portion can directly interface to T1, E1, or Functionality 64KCC synchronization interfaces as well as source Internal Software-Selectable Receive and the SSM in T1 and E1 modes. The DS26504 can Transmit Side Termination for translate between any of the supported inbound 75 /100 /110 /120 /133 synchronization clock rates to any supported Monitor Mode for Bridging Applications outbound rate. The DS26504 can also accept an 8kHz Accepts 16.384MHz, 12.8MHz, 8.192MHz, as well as a 19.44MHz reference clock. A separate 4.096MHz, 2.048MHz, or 1.544MHz Master output is provided to source a 6312kHz clock. The Clock device is controlled through a parallel, serial, or 64kHz, 8kHz, and 400Hz Outputs in Composite hardware controller port. Clock Mode 8-Bit Parallel Control Port, Multiplexed or APPLICATIONS Nonmultiplexed, Intel or Motorola Serial (SPI) Control Port and Hardware Control BITS Timing Mode Rate Conversion Provides LOS, AIS, and LOF Indications through Hardware Output Pins FEATURES Fast Transmitter Output Disable through Device Accepts 8kHz and 19.44MHz References in Pin for Protection Switching Addition to T1, E1, and 64kHz Composite Clock IEEE 1149.1 JTAG Boundary Scan GR378 Composite Clock Compliant 3.3V Supply with 5V Tolerant Inputs and G.703 2048kHz Synchronization Interface Outputs Compliant Pin and Software Compatible with the DS26502 G.703 64kHz Option A & B Centralized Clock and DS26503 Synchronization Interface Compliant G.703 64kHz Japanese Composite Clock Synchronization Interface Compliant ORDERING INFORMATION G.703 6312kHz Japanese Synchronization Interface Compliant PART TEMP RANGE PIN-PACKAGE Interfaces to Standard T1/J1 (1.544MHz) and E1 DS26504L 0C to +70C 64 LQFP (2.048MHz) Interface to CMI-Coded T1/J1 and E1 DS26504LN -40C to +85C 64 LQFP T1/E1 Transmit Payload Clock Output Short- and Long-Haul Line Interface Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 129 REV: 072308 DS26504 T1/E1/J1/64KCC BITS Element TABLE OF CONTENTS 1. FEATURES.......................................................................................................................7 1.1 GENERAL .....................................................................................................................................7 1.2 LINE INTERFACE ...........................................................................................................................7 1.3 JITTER ATTENUATOR (T1/E1 MODES ONLY) ..................................................................................7 1.4 FRAMER/FORMATTER ...................................................................................................................8 1.5 TEST AND DIAGNOSTICS ...............................................................................................................8 1.6 CONTROL PORT............................................................................................................................8 2. SPECIFICATIONS COMPLIANCE ...................................................................................9 3. BLOCK DIAGRAMS .......................................................................................................11 4. PIN FUNCTION DESCRIPTION .....................................................................................14 4.1 TRANSMIT PLL ...........................................................................................................................14 4.2 TRANSMIT SIDE ..........................................................................................................................14 4.3 RECEIVE SIDE ............................................................................................................................15 4.4 CONTROLLER INTERFACE............................................................................................................16 4.5 JTAG.........................................................................................................................................20 4.6 LINE INTERFACE .........................................................................................................................21 4.7 POWER ......................................................................................................................................21 5. PINOUT...........................................................................................................................22 6. HARDWARE CONTROLLER INTERFACE....................................................................25 6.1 TRANSMIT CLOCK SOURCE .........................................................................................................25 6.2 INTERNAL TERMINATION..............................................................................................................25 6.3 LINE BUILD-OUT .........................................................................................................................26 6.4 RECEIVER OPERATING MODES....................................................................................................27 6.5 TRANSMITTER OPERATING MODES..............................................................................................27 6.6 MCLK PRE-SCALER ...................................................................................................................28 6.7 PAYLOAD CLOCK OUTPUT...........................................................................................................28 6.8 OTHER HARDWARE CONTROLLER MODE FEATURES ....................................................................29 7. PROCESSOR INTERFACE............................................................................................30 7.1 PARALLEL PORT FUNCTIONAL DESCRIPTION................................................................................30 7.2 SPI SERIAL PORT INTERFACE FUNCTIONAL DESCRIPTION............................................................30 7.2.1 Clock Phase and Polarity..................................................................................................................... 30 7.2.2 Bit Order............................................................................................................................................... 30 7.2.3 Control Byte ......................................................................................................................................... 30 7.2.4 Burst Mode........................................................................................................................................... 30 7.2.5 Register Writes..................................................................................................................................... 31 7.2.6 Register Reads .................................................................................................................................... 31 7.3 REGISTER MAP...........................................................................................................................32 7.3.1 Power-Up Sequence............................................................................................................................ 34 7.3.2 Test Reset Register ............................................................................................................................. 34 7.3.3 Mode Configuration Register ............................................................................................................... 35 7.4 INTERRUPT HANDLING ................................................................................................................37 7.5 STATUS REGISTERS....................................................................................................................37 7.6 INFORMATION REGISTERS...........................................................................................................38 7.7 INTERRUPT INFORMATION REGISTERS .........................................................................................39 2 of 129