19-5856 Rev 4 5/11 DS26514 4-Port T1/E1/J1 Transceiver General Description Features Four Complete T1, E1, or J1 Long-Haul/ The DS26514 is a 4-port framer and line interface Short-Haul Transceivers (LIU Plus Framer) unit (LIU) combination for T1, E1, J1 applications. Each port is independently configurable, supporting Independent T1, E1, or J1 Selections for Each Transceiver both long-haul and short-haul lines. The DS26514 single-chip transceiver (SCT) is software and pinout Fully Internal Impedance Match, No External compatible with the 8-port DS26518. It is nearly Resistor software compatible with the DS26528 and its Software-Selectable Transmit- and Receive- derivatives. Side Termination for 100 T1 Twisted Pair, Applications 110 J1 Twisted Pair, 120 E1 Twisted Pair, Routers and 75 E1 Coaxial Applications Channel Service Units (CSUs) Hitless Protection Switching Data Service Units (DSUs) Crystal-Less Jitter Attenuators Can Be Muxes Selected for Transmit or Receive Path Jitter Switches Attenuator Meets ETS CTR 12/13, ITU-T Channel Banks G.736, G.742, G.823, and AT&T Pub 62411 T1/E1 Test Equipment External Master Clock Can Be Multiple of Functional Diagram 2.048MHz or 1.544MHz for T1/J1 or E1 Operation This Clock is Internally Adapted DS26514 for T1 or E1 Usage in the Host Mode T1/E1/J1 Receive-Signal Level Indication from -2.5dB NETWORK to -36dB in T1 Mode and -2.5dB to -44dB in E1 Mode in Approximate 2.5dB Increments T1/J1/E1 BACKPLANE Transmit Open- and Short-Circuit Detection x4 Transceiver TDM LIU LOS in Accordance with G.775, ETS 300 233, and T1.231 Transmit Synchronizer Flexible Signaling Extraction and Insertion Using Either the System Interface or Microprocessor Port Ordering Information Alarm Detection and Insertion PART TEMP RANGE PIN-PACKAGE T1 Framing Formats of D4, SLC-96, and ESF DS26514GN -40C to +85C 256 TE-CSBGA J1 Support DS26514GN+ 256 TE-CSBGA -40C to +85C E1 G.704 and CRC-4 Multiframe +Denotes a lead(Pb)-free/RoHS compliant package. T1-to-E1 Conversion Features continued in Section 2. Maxim Integrated Products 1 Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxims website at www.maxim-ic.com. DS26514 4-Port T1/E1/J1 Transceiver TABLE OF CONTENTS 1. DETAILED DESCRIPTION ................................................................................................. 9 2. FEATURE HIGHLIGHTS .................................................................................................. 10 2.1 GENERAL ................................................................................................................................... 10 2.2 LINE INTERFACE ......................................................................................................................... 10 2.3 CLOCK SYNTHESIZERS ............................................................................................................... 10 2.4 JITTER ATTENUATOR .................................................................................................................. 10 2.5 FRAMER/FORMATTER ................................................................................................................. 11 2.6 SYSTEM INTERFACE ................................................................................................................... 11 2.7 HDLC CONTROLLERS ................................................................................................................. 12 2.8 TEST AND DIAGNOSTICS ............................................................................................................. 12 2.9 MICROCONTROLLER PARALLEL PORT .......................................................................................... 12 2.10 SLAVE SERIAL PERIPHERAL INTERFACE (SPI) FEATURES .......................................................... 12 3. APPLICATIONS ............................................................................................................... 13 4. SPECIFICATIONS COMPLIANCE ................................................................................... 14 5. ACRONYMS AND GLOSSARY ....................................................................................... 16 6. MAJOR OPERATING MODES ......................................................................................... 17 7. BLOCK DIAGRAMS ......................................................................................................... 18 8. PIN DESCRIPTIONS ........................................................................................................ 20 8.1 PIN FUNCTIONAL DESCRIPTION ................................................................................................... 20 9. FUNCTIONAL DESCRIPTION ......................................................................................... 28 9.1 PROCESSOR INTERFACE ............................................................................................................. 28 9.1.1 SPI Serial Port Mode....................................................................................................................... 28 9.1.2 SPI Functional Timing Diagrams ..................................................................................................... 28 9.2 CLOCK STRUCTURE .................................................................................................................... 31 9.2.1 Backplane Clock Generation ........................................................................................................... 31 9.2.2 CLKO Output Clock Generation ...................................................................................................... 32 9.3 RESETS AND POWER-DOWN MODES ........................................................................................... 33 9.4 INITIALIZATION AND CONFIGURATION ........................................................................................... 34 9.4.1 Example Device Initialization and Sequence ................................................................................... 34 9.5 GLOBAL RESOURCES.................................................................................................................. 34 9.6 PER-PORT RESOURCES.............................................................................................................. 34 9.7 DEVICE INTERRUPTS .................................................................................................................. 34 9.8 SYSTEM BACKPLANE INTERFACE ................................................................................................. 36 9.8.1 Elastic Stores .................................................................................................................................. 36 9.8.2 IBO Multiplexing .............................................................................................................................. 39 9.8.3 H.100 (CT Bus) Compatibility .......................................................................................................... 45 9.8.4 Transmit and Receive Channel Blocking Registers.......................................................................... 47 9.8.5 Transmit Fractional Support (Gapped Clock Mode) ......................................................................... 47 9.8.6 Receive Fractional Support (Gapped Clock Mode) .......................................................................... 47 9.9 FRAMERS ................................................................................................................................... 48 9.9.1 T1 Framing ..................................................................................................................................... 48 9.9.2 E1 Framing ..................................................................................................................................... 51 9.9.3 T1 Transmit Synchronizer ............................................................................................................... 53 9.9.4 Signaling ......................................................................................................................................... 54 9.9.5 T1 Data Link ................................................................................................................................... 59 9.9.6 E1 Data Link ................................................................................................................................... 61 9.9.7 Maintenance and Alarms................................................................................................................. 62 19-5856 Rev 4 5/11 2 of 305