DS26521 Single T1/E1/J1 Transceiver www.maxim-ic.com GENERAL DESCRIPTION FEATURES Complete T1, E1, or J1 Long-Haul/Short-Haul The DS26521 is a single-channel framer and line Transceiver (LIU plus Framer) interface unit (LIU) combination for T1, E1, and J1 applications. Each channel is independently Internal Software-Selectable Transmit- and configurable, supporting both long-haul and short-haul Receive-Side Termination for 100 T1 Twisted lines. Pair, 110 J1 Twisted Pair, 120 E1 Twisted Pair, and 75 E1 Coaxial Applications APPLICATIONS Crystal-Less Jitter Attenuator can be Selected for Transmit or Receive Path Jitter Attenuator Routers Meets ETS CTR 12/13, ITU-T G.736, G.742, Channel Service Units (CSUs) G.823, and AT&T Pub 62411 Data Service Units (DSUs) External Master Clock can be Multiple of Muxes 2.048MHz or 1.544MHz for T1/J1 or E1 Switches Operation This Clock is Internally Adapted for T1 or E1 Usage in the Host Mode Channel Banks T1/E1 Test Equipment Receive-Signal Level Indication from -2.5dB to -36dB in T1 Mode and -2.5dB to -44dB in E1 Mode in Approximate 2.5dB Increments FUNCTIONAL DIAGRAM Transmit Open- and Short-Circuit Detection LIU LOS in Accordance with G.775, ETS 300 DS26521 T1/E1/J1 233, and T1.231 NETWORK Transmit Synchronizer Flexible Signaling Extraction and Insertion T1/J1/E1 Using Either the System Interface or BACKPLANE Transceiver Microprocessor Port TDM Alarm Detection and Insertion T1 Framing Formats of D4, SLC-96, and ESF J1 Support E1 G.704 and CRC-4 Multiframe ORDERING INFORMATION Controlled by 8-Bit Parallel Port Interface or Serial Peripheral Interface (SPI) PART TEMP RANGE PIN-PACKAGE DS26521LN -40C to +85C 64 LQFP Features Continued in Section 2. DS26521LN+ -40C to +85C 64 LQFP + Denotes lead-free/RoHS compliant device. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 258 REV: 111606 DS26521 Single T1/E1/J1 Transceiver TABLE OF CONTENTS 1. DETAILED DESCRIPTION...............................................................................................9 1.1 MAJOR OPERATING MODES.............................................................................................................9 2. FEATURE HIGHLIGHTS ................................................................................................10 2.1 GENERAL......................................................................................................................................10 2.2 LINE INTERFACE............................................................................................................................10 2.3 CLOCK SYNTHESIZER ....................................................................................................................10 2.4 JITTER ATTENUATOR .....................................................................................................................10 2.5 FRAMER/FORMATTER....................................................................................................................10 2.6 SYSTEM INTERFACE ......................................................................................................................11 2.7 HDLC CONTROLLERS ...................................................................................................................12 2.8 TEST AND DIAGNOSTICS ................................................................................................................12 2.9 MICROCONTROLLER PARALLEL PORT.............................................................................................12 2.10 SLAVE SERIAL PERIPHERAL INTERFACE (SPI) FEATURES ............................................................12 3. APPLICATIONS..............................................................................................................13 4. SPECIFICATIONS COMPLIANCE .................................................................................14 5. ACRONYMS AND GLOSSARY......................................................................................16 6. BLOCK DIAGRAMS .......................................................................................................17 7. PIN DESCRIPTIONS ......................................................................................................19 7.1 PIN FUNCTIONAL DESCRIPTION......................................................................................................19 8. FUNCTIONAL DESCRIPTION........................................................................................25 8.1 MICROPROCESSOR INTERFACE......................................................................................................25 8.1.1 Parallel Port Mode................................................................................................................................ 25 8.1.2 SPI Serial Port Mode............................................................................................................................ 25 8.1.3 SPI Functional Timing Diagrams ......................................................................................................... 25 8.2 CLOCK STRUCTURE.......................................................................................................................28 8.2.1 Backplane Clock Generation ............................................................................................................... 28 8.3 RESETS AND POWER-DOWN MODES..............................................................................................29 8.4 INITIALIZATION AND CONFIGURATION..............................................................................................30 8.4.1 Example Device Initialization Sequence.............................................................................................. 30 8.5 GLOBAL RESOURCES ....................................................................................................................30 8.6 PORT RESOURCES ........................................................................................................................30 8.7 DEVICE INTERRUPTS .....................................................................................................................30 8.8 SYSTEM BACKPLANE INTERFACE ...................................................................................................32 8.8.1 Elastic Stores ....................................................................................................................................... 32 8.8.2 IBO Multiplexer..................................................................................................................................... 35 8.8.3 H.100 (CT Bus) Compatibility .............................................................................................................. 36 8.8.4 Receive and Transmit Channel Blocking Registers............................................................................. 37 8.8.5 Transmit Fractional Support (Gapped Clock Mode) ............................................................................ 37 8.8.6 Receive Fractional Support (Gapped Clock Mode) ............................................................................. 37 8.9 FRAMERS......................................................................................................................................38 8.9.1 T1 Framing........................................................................................................................................... 38 8.9.2 E1 Framing........................................................................................................................................... 41 8.9.3 T1 Transmit Synchronizer.................................................................................................................... 43 8.9.4 Signaling .............................................................................................................................................. 44 8.9.5 T1 Data Link......................................................................................................................................... 48 8.9.6 E1 Data Link......................................................................................................................................... 50 8.9.7 Maintenance and Alarms ..................................................................................................................... 51 2 of 258