DS3112+ Analog Devices

DS3112 TEMPE T3/E3 Multiplexer 3.3V T3/E3 Framer and M13/E13/G.747 Mux www.maxim-ic.com FEATURES FUNCTIONAL DIAGRAM Operates as M13 or E13 Multiplexer or as Stand-Alone T3 or E3 Framer T1/E1 Flexible Multiplexer can be Programmed for T2/E2 T1/E1 Multiple Configurations Including: T1/E1 M13 Multiplexing (28 T1 Lines into a T3 T1/E1 Data Stream) E13 Multiplexing (16 E1 Lines into an E3 T3/E3 Data Stream) E1 to T3 Multiplexing (21 E1 Lines into a T3 T1/E1 Data Stream) T1/E1 Two T1/E1 Drop and Insert Ports T2/E2 T1/E1 DS3112 Supports T3 C-Bit Parity Mode T1/E1 B3ZS/HDB3 Encoder and Decoder Generates and Detects T3/E3 Alarms Generates and Detects T2/E2 Alarms APPLICATIONS Integrated HDLC Controller Handles LAPD Wide Area Network Access Equipment Messages Without Host Intervention PBXs Integrated FEAC Controller Access Concentrators Integrated BERT Supports Performance Digital Cross-Connect Systems Monitoring Switches T3/E3 and T1/E1 Diagnostic (Tx to Rx), Line Routers (Rx to Tx), and Payload Loopback Optical Multiplexers Supported ADMs Nonmultiplexed or Multiplexed 16-Bit Test Equipment Control Port (with Optional 8-Bit Mode) ORDERING INFORMATION 3.3V Supply with 5V Tolerant I/O Available in 256-Pin 1.27mm Pitch PBGA PART TEMP RANGE PIN-PACKAGE Package DS3112 0C to +70C 256 PBGA IEEE 1149.1 JTAG Support DS3112+ 256 PBGA 0C to +70C DS3112N 256 PBGA -40C to +85C DS3112N+ -40C to +85C 256 PBGA +Denotes lead-free/RoHS-compliant package. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 133 REV: 092706 DS3112 TABLE OF CONTENTS 1 DETAILED DESCRIPTION 7 1.1 APPLICABLE STANDARDS ..............................................................................................................8 1.2 MAIN DS3112 TEMPE FEATURES................................................................................................9 1.2.1 General Features ................................................................................................................................... 9 1.2.2 T3/E3 Framer ......................................................................................................................................... 9 1.2.3 T2/E2 Framer ......................................................................................................................................... 9 1.2.4 HDLC Controller..................................................................................................................................... 9 1.2.5 FEAC Controller..................................................................................................................................... 9 1.2.6 BERT.................................................................................................................................................... 10 1.2.7 Diagnostics........................................................................................................................................... 10 1.2.8 Control Port .......................................................................................................................................... 10 1.2.9 Packaging and Power .......................................................................................................................... 10 2 PIN DESCRIPTION 14 2.2 CPU BUS SIGNAL DESCRIPTION .................................................................................................19 2.3 T3/E3 RECEIVE FRAMER SIGNAL DESCRIPTION...........................................................................21 2.4 T3/E3 TRANSMIT FORMATTER SIGNAL DESCRIPTION...................................................................23 2.5 LOW-SPEED (T1 OR E1) RECEIVE PORT SIGNAL DESCRIPTION....................................................25 2.6 LOW-SPEED (T1 OR E1) TRANSMIT PORT SIGNAL DESCRIPTION..................................................26 2.7 HIGH-SPEED (T3 OR E3) RECEIVE PORT SIGNAL DESCRIPTION ...................................................28 2.8 HIGH-SPEED (T3 OR E3) TRANSMIT PORT SIGNAL DESCRIPTION .................................................28 2.9 JTAG SIGNAL DESCRIPTION .......................................................................................................29 2.10 SUPPLY, TEST, RESET, AND MODE SIGNAL DESCRIPTION............................................................29 3 MEMORY MAP 31 4 MASTER DEVICE CONFIGURATION AND STATUS/INTERRUPT 33 4.1 MASTER RESET AND ID REGISTER DESCRIPTION.........................................................................33 4.2 MASTER CONFIGURATION REGISTERS DESCRIPTION ...................................................................34 4.3 MASTER STATUS AND INTERRUPT REGISTER DESCRIPTION..........................................................38 4.3.1 Status Registers................................................................................................................................... 38 4.3.2 MSR ..................................................................................................................................................... 39 4.4 TEST REGISTER DESCRIPTION ....................................................................................................47 5 T3/E3 FRAMER 48 5.1 T3/E3 LINE LOOPBACK ...............................................................................................................48 5.2 T3/E3 DIAGNOSTIC LOOPBACK ...................................................................................................48 5.3 T3/E3 PAYLOAD LOOPBACK........................................................................................................48 5.4 T3/E3 FRAMER CONTROL REGISTER DESCRIPTION .....................................................................49 5.5 T3/E3 FRAMER STATUS AND INTERRUPT REGISTER DESCRIPTION ...............................................53 5.6 T3/E3 PERFORMANCE ERROR COUNTERS ..................................................................................59 6 M13/E13/G.747 MULTIPLEXER AND T2/E2/G.747 FRAME 62 6.1 T1/E1 AIS GENERATION.............................................................................................................62 6.2 T2/E2/G.747 FRAMER CONTROL REGISTER DESCRIPTION ..........................................................62 6.3 T2/E2/G.747 FRAMER STATUS AND INTERRUPT REGISTER DESCRIPTION ....................................64 6.4 T1/E1 AIS GENERATION CONTROL REGISTER DESCRIPTION .......................................................68 7 T1/E1 LOOPBACK AND DROP AND INSERT FUNCTIONALITY 70 7.1 T1/E1 LINE LOOPBACK ...............................................................................................................70 7.2 T1/E1 DIAGNOSTIC LOOPBACK ...................................................................................................70 7.3 T1 LINE LOOPBACK COMMAND....................................................................................................70 7.4 T1/E1 DROP AND INSERT............................................................................................................70 7.5 T1/E1 LOOPBACK CONTROL REGISTER DESCRIPTION .................................................................71 2 of 133