PRODUCT BRIEF DS3177 DS3/E3 Single-Chip Transceiver FEATURES GENERAL DESCRIPTION Single-Chip Transceiver for DS3 and E3 The DS3177 combines a DS3/E3 framer and an LIU Performs Receive Clock/Data Recovery and (single-chip transceiver) to interface to a DS3/E3 Transmit Waveshaping for DS3 and E3 physical copper line. Jitter Attenuator can be Placed Either in the Receive or Transmit Path APPLICATIONS Interfaces to 75 Coaxial Cable at Lengths Up to Access Concentrators Multiservice Access 380 Meters or 1246 Feet (DS3), or 440 Meters or Platforms (MSAPs) Routers and Switches 1443 Feet (E3) SONET/SDH ADM Multiservice Protocol Uses 1:2 Transformers on Both Tx and Rx Platform (MSPPs) SONET/SDH Muxes On-Chip DS3 (M23 or C-Bit) and E3 (G.751 or G.832) Framer PBXs Test Equipment Built-In HDLC Controller with 256-Byte FIFO for PDH Multiplexer/ Digital Cross Connect the Insertion/Extraction of DS3 PMDL, G.751 Sn Demultiplexer Integrated-Access Device Bit, and G.832 NR/GC Bytes (IAD) On-Chip BERT for PRBS and Repetitive Pattern Generation, Detection and Analysis Large Performance-Monitoring Counters for ORDERING INFORMATION Accumulation Intervals of At Least 1 Second PART TEMP RANGE PIN-PACKAGE Flexible Overhead Insertion/Extraction Port for DS3177+ 0C to +70C 100 CSBGA DS3, E3 Framers DS3177N+ -40C to +85C 100 CSBGA Loopbacks Include Line, Diagnostic, Framer, +Denotes a lead(Pb)-free/RoHS compliant package. Payload, and Analog with Capabilities to Insert AIS in the Directions Away from Loopback Directions FUNCTIONAL DIAGRAM Integrated Clock Rate Adapter to Generate the Remaining Internally Required 44.736MHz (DS3) and 34.368MHz (E3) from a Single-Clock Reference Source CLAD Reference Clock can be 44.736MHz, 34.368MHz, 77.76MHz, 51.84MHz, or 19.44MHz DS3/ DS3/E3 E3 FRAMER/ SYSTEM Software Compatible with DS3171DS3174 SCT DS3/E3 LINE LIU FORMATTER BACKPLANE Product Family 8-/16-Bit Parallel and Slave SPI Serial ( 10Mbps) Microprocessor Interface DS3177 Low-Power (0.5W) 3.3V Operation (5V Tolerant I/O) 100-Pin Small 11mm x 11mm (1mm) CSBGA Industrial Temperature Operation: -40C to +85C IEEE 1149.1 JTAG Test Port Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maximintegrated.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at 19-6798 Rev 0 9/13 1 -888-629-4642, or visit Maxim Integrateds website at www.m aximintegrated.com. 1 of 230 DS3177 DS3/E3 Single-Chip Transceiver TABLE OF CONTENTS 1 DETAILED DESCRIPTION 10 2 BLOCK DIAGRAMS 10 3 APPLICATIONS 12 4 FEATURE DETAILS 13 4.1 GLOBAL FEATURES ........................................................................................................................................ 13 4.2 RECEIVE DS3/E3 LIU FEATURES ................................................................................................................... 13 4.3 JITTER ATTENUATOR FEATURES ..................................................................................................................... 13 4.4 RECEIVE DS3/E3 FRAMER FEATURES ............................................................................................................ 13 4.5 TRANSMIT DS3/E3 FORMATTER FEATURES .................................................................................................... 14 4.6 TRANSMIT DS3/E3 LIU FEATURES ................................................................................................................. 14 4.7 CLOCK RATE ADAPTER FEATURES ................................................................................................................. 14 4.8 HDLC CONTROLLER FEATURES ..................................................................................................................... 14 4.9 FEAC CONTROLLER FEATURES ..................................................................................................................... 14 4.10 TRAIL TRACE BUFFER FEATURES ................................................................................................................... 15 4.11 BIT ERROR-RATE TESTER (BERT) FEATURES ................................................................................................ 15 4.12 LOOPBACK FEATURES ................................................................................................................................... 15 4.13 MICROPROCESSOR INTERFACE FEATURES ..................................................................................................... 15 4.14 SLAVE SERIAL PERIPHERAL INTERFACE (SPI) FEATURES ................................................................................ 15 4.15 TEST FEATURES ............................................................................................................................................ 15 5 STANDARDS COMPLIANCE 16 6 ACRONYMS AND GLOSSARY 17 7 MAJOR OPERATIONAL MODES 18 7.1 DS3/E3 FRAMED LIU MODE .......................................................................................................................... 18 7.2 DS3/E3 UNFRAMED LIU MODE ...................................................................................................................... 20 7.3 DS3/E3 FRAMED POS/NEG MODE ............................................................................................................... 21 7.4 DS3/E3 UNFRAMED POS/NEG MODE ........................................................................................................... 22 7.5 DS3/E3 FRAMED UNI MODE ......................................................................................................................... 23 7.6 DS3/E3 UNFRAMED UNI MODE ..................................................................................................................... 24 8 PIN DESCRIPTIONS 25 8.1 SHORT PIN DESCRIPTIONS ............................................................................................................................. 25 8.2 DETAILED PIN DESCRIPTIONS......................................................................................................................... 27 8.3 PIN FUNCTIONAL TIMING ................................................................................................................................ 37 8.3.1 Line IO .................................................................................................................................................. 37 8.3.2 DS3/E3 Framing Overhead Functional Timing .................................................................................... 40 8.3.3 DS3/E3 Serial Data Interface ............................................................................................................... 41 8.3.4 Microprocessor Interface Functional Timing ........................................................................................ 43 8.3.5 JTAG Functional Timing....................................................................................................................... 50 9 INITIALIZATION AND CONFIGURATION 51 9.1 MONITORING AND DEBUGGING ....................................................................................................................... 52 10 FUNCTIONAL DESCRIPTION 53 10.1 PROCESSOR BUS INTERFACE ......................................................................................................................... 53 10.1.1 SPI Serial Port Mode ............................................................................................................................ 53 10.1.2 8/16 Bit Bus Widths .............................................................................................................................. 53 10.1.3 Ready Signal ( ) ............................................................................................................................. 53 10.1.4 Byte Swap Modes ................................................................................................................................ 53 10.1.5 Read-Write/Data Strobe Modes ........................................................................................................... 53 10.1.6 Clear on Read/Clear on Write Modes .................................................................................................. 53 10.1.7 Interrupt and Pin Modes ....................................................................................................................... 54 10.1.8 Interrupt Structure ................................................................................................................................ 54 10.2 CLOCKS ........................................................................................................................................................ 55 10.2.1 Line Clock Modes ................................................................................................................................. 55 10.2.2 Sources of Clock Output Pin Signals ................................................................................................... 57 2 of 230