+ DS32506/DS32508/DS32512 6-/8-/12-Port DS3/E3/STS-1 LIU www.maxim-ic.com FEATURES GENERAL DESCRIPTION Pin-Compatible Family of Products The DS32506 (6 port), DS32508 (8 port), and Each Port Independently Configurable DS32512 (12 port) line interface units (LIUs) are Receive Clock and Data Recovery for Up to 457 highly integrated, low-power, feature-rich LIUs for meters (1500 feet) of 75 Coaxial Cable DS3, E3, and STS-1 applications. Each LIU port in Standards-Compliant Transmit Waveshaping these devices has independent receive and transmit Uses 1:1 Transformers on Both Tx and Rx paths, a jitter attenuator, full-featured pattern Three Control Interface Options: 8/16-Bit generator and detector, performance-monitoring Parallel, SPI, and Hardware Mode counters, and a complete set of loopbacks. An on- Jitter Attenuators (One Per Port) Can be Placed chip clock adapter generates all line-rate clocks from in the Receive Path or the Transmit Path a single input clock. Ports are independently software configurable for DS3, E3, and STS-1 and can be Jitter Attenuators Have Provisionable Buffer individually powered down. Control interface options Depth: 16, 32, 64, or 128 Bits include 8-bit parallel, SPI, and hardware mode. Built-In Clock Adapter Generates All Line-Rate Clocks from a Single Input Clock (DS3, E3, STS-1, APPLICATIONS 12.8MHz, 19.44MHz, 38.88MHz, 77.76MHz) Per-Port Programmable Internal Line Termination SONET/SDH and PDH Digital Cross- Requiring Only External Transformers Multiplexers Connects High-Impedance Tx and Rx, Even When V = 0, ATM and Frame Relay Access Concentrators DD Enables Hot-Swappable, 1:1 and 1+1 Board Equipment CSUs/DSUs Redundancy Without Relays WAN Routers and PBXs Per-Port BERT for PRBS and Repetitive Pattern Switches DSLAMs Generation and Detection Tx and Rx Open and Short Detection Circuitry FUNCTIONAL DIAGRAM Transmit Driver Monitor Circuitry Receive Loss-of-Signal (LOS) Monitoring EACH LIU Compliant with ANSI T1.231 and ITU G.775 LINE IN RECEIVE Automatic Data Squelching on Receive LOS RXP CLK DS3, E3, CLOCK Large Line Code Performance-Monitoring RXN DATA OR STS-1 AND DATA Counters for Accumulation Intervals Up to 1s Local and Remote Loopbacks CONTROL Dallas Transmit Common Clock Option Semiconductor AND Power-Down Capability for Unused Ports DS325xx STATUS Low-Power 1.8V/3.3V Operation (5V Tolerant I/O) Industrial Temperature Range: -40C to +85 C LINE OUT TRANSMIT TXP CLK DS3, E3, CLOCK Small Package: 23mm x 23mm, 484-Pin BGA TXN DATA OR STS-1 AND DATA IEEE 1149.1 JTAG Support ORDERING INFORMATION PART LIUs TEMP RANGE PIN-PACKAGE DS32506 6 0C to +70C 484 BGA DS32506N 6 -40C to +85C 484 BGA DS32508 8 0C to +70C 484 BGA DS32508N 8 -40C to +85C 484 BGA DS32512 12 0C to +70C 484 BGA DS32512N 12 -40C to +85C 484 BGA Note: Add the + suffix for the lead-free package option. Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 130 REV: 103008 DS32506/DS32508/DS32512 TABLE OF CONTENTS 1. STANDARDS COMPLIANCE .............................................................................................6 2. BLOCK DIAGRAM ..............................................................................................................7 3. APPLICATION EXAMPLE ..................................................................................................8 4. DETAILED DESCRIPTION..................................................................................................9 5. DETAILED FEATURES.....................................................................................................11 5.1 GLOBAL FEATURES .......................................................................................................................11 5.2 RECEIVER.....................................................................................................................................11 5.3 TRANSMITTER ...............................................................................................................................11 5.4 JITTER ATTENUATOR.....................................................................................................................11 5.5 BIT ERROR-RATE TESTER (BERT) FEATURES ...............................................................................12 5.6 CLOCK ADAPTER...........................................................................................................................12 5.7 PARALLEL MICROPROCESSOR INTERFACE FEATURES.....................................................................12 5.8 SPI SERIAL MICROPROCESSOR INTERFACE FEATURES ..................................................................12 5.9 MISCELLANEOUS FEATURES..........................................................................................................12 5.10 TEST FEATURES............................................................................................................................12 5.11 LOOPBACK FEATURES...................................................................................................................12 6. CONTROL INTERFACE MODES......................................................................................13 7. PIN DESCRIPTIONS .........................................................................................................14 7.1 SHORT PIN DESCRIPTIONS ............................................................................................................14 7.2 DETAILED PIN DESCRIPTIONS ........................................................................................................17 8. FUNCTIONAL DESCRIPTION ..........................................................................................24 8.1 LIU MODE ....................................................................................................................................24 8.2 TRANSMITTER ...............................................................................................................................24 8.2.1 Transmit Clock .................................................................................................................................... 24 8.2.2 Framer Interface Format and the B3ZS/HDB3 Encoder..................................................................... 24 8.2.3 Error Insertion ..................................................................................................................................... 24 8.2.4 AIS Generation.................................................................................................................................... 25 8.2.5 Waveshaping ...................................................................................................................................... 25 8.2.6 Line Build-Out ..................................................................................................................................... 25 8.2.7 Line Driver........................................................................................................................................... 25 8.2.8 Interfacing to the Line ......................................................................................................................... 25 8.2.9 Driver Monitor and Output Failure Detection ...................................................................................... 26 8.2.10 Power-Down........................................................................................................................................ 26 8.2.11 Jitter Generation (Intrinsic).................................................................................................................. 26 8.2.12 Jitter Transfer...................................................................................................................................... 26 8.3 RECEIVER.....................................................................................................................................30 8.3.1 Interfacing to the Line ......................................................................................................................... 30 8.3.2 Optional Preamp ................................................................................................................................. 30 8.3.3 Automatic Gain Control (AGC) and Adaptive Equalizer ..................................................................... 30 8.3.4 Clock and Data Recovery (CDR)........................................................................................................ 31 8.3.5 Loss-of-Signal (LOS) Detector............................................................................................................ 31 8.3.6 Framer Interface Format and the B3ZS/HDB3 Decoder .................................................................... 32 8.3.7 Power-Down........................................................................................................................................ 33 8.3.8 Input Failure Detection........................................................................................................................ 33 8.3.9 Jitter and Wander Tolerance............................................................................................................... 34 8.3.10 Jitter Transfer...................................................................................................................................... 35 8.4 JITTER ATTENUATOR.....................................................................................................................35 8.5 BERT...........................................................................................................................................36 2 of 130