Rev: 063008 DS33X162/DS33X161/DS33X82/DS33X81/ DS33X42/DS33X41/DS33X11/DS33W41/DS33W11 Ethernet Over PDH Mapping Devices General Description Features The DS33X162 family of semiconductor devices 10/100/1000 IEEE 802.3 MAC (MII/RMII/GMII) extend 10/100/1000Mbps Ethernet LAN segments by with Autonegotiation and Flow Control encapsulating MAC frames in GFP-F, HDLC, cHDLC, GFP-F/LAPS/HDLC/cHDLC Encapsulation or X.86 (LAPS) for transmission over PDH/TDM data VCAT/LCAS Link Aggregation for Up to 16 streams. The devices support the Ethernet over PDH Links (EoPDH) standards for the delivery of Ethernet Supports Up to 200ms Differential Delay Access Services, including eLAN, eLINE, and VLAN. The multiport devices support VCAT/LCAS for Quality of Service (QoS) Support dynamic link aggregation. The serial links support VLAN, Q-in-Q, 802.1p, and DSCP Support bidirectional synchronous interconnect up to 52Mbps Ethernet Bridging and Filtering over xDSL, T1/E1/J1, T3/E3, or V.35/Optical. Add/Drop OAM Frames from P Interface The devices perform store-and-forward of frames Traffic Shaping Through CIR/CBS Policing with Ethernet traffic conditioning and bridging External 256Mb, 125MHz DDR SDRAM Buffer functions at wire speed. The programmability of Parallel and SPI Microprocessor Interfaces classification, priority queuing, encapsulation, and 1.8V, 2.5V, 3.3V Supplies bundling allows great flexibility in providing various Ethernet services. OAM flows can be extracted and IEEE 1149.1 JTAG Support inserted by an external processor to manage the Features continued in Section 2. Ethernet service. The voice ports of the DS33W41 and DS33W11 Ordering Information easily connect to external codecs for integrated voice PORTS PIN- and data service applications. PART PACKAGE TDM ETHERNET VOICE DS33X162+ 16 2 0 256 CSBGA Applications DS33X161+ 16 1 0 256 CSBGA Bonded Transparent LAN Service DS33X82+ 8 2 0 256 CSBGA LAN Extension DS33X81+ 8 1 0 256 CSBGA Ethernet Delivery Over T1/E1/J1, T3/E3, DS33X42+ 4 2 0 256 CSBGA OC-1/EC-1, G.SHDSL, or HDSL2/4 DS33X41+ 4 1 0 256 CSBGA DS33X11+ 1 1 0 144 CSBGA Functional Diagram DS33W41+ 4 1 1 256 CSBGA PROCESSOR DS33W11+ 1 1 1 256 CSBGA Note: All devices are specified over the -40C to +85C industrial 8-BIT & SPI P INTERFACE QoS operating temperature range. POLICY WAN CLAD ENET +Denotes a lead-free/RoHS-compliant package. TDM LIU/ SERIAL PHYs PORTS FRAMER BUFFER MANAGER BRIDGING SPI is a trademark of Motorola, Inc. SDRAM CONTROLLER VOICE PORT DS33X162 DDR SDRAM Maxim Integrated Products 1 Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxims website at www.maxim-ic.com. GFP/ LAPS/ HDLC TRAFFIC MGMT MACs DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 Table of Contents 1. DETAILED DESCRIPTION ..............................................................................................................9 2. FEATURE HIGHLIGHTS................................................................................................................10 2.1 GENERAL......................................................................................................................................10 2.2 VCAT/LCAS LINK AGGREGATION (INVERSE MULTIPLEXING) ..........................................................10 2.3 HDLC...........................................................................................................................................10 2.3.1 cHDLC.................................................................................................................................................. 10 2.4 GFP-F..........................................................................................................................................11 2.5 X.86 SUPPORT .............................................................................................................................11 2.6 DDR SDRAM INTERFACE.............................................................................................................11 2.7 MAC INTERFACES.........................................................................................................................11 2.7.1 Ethernet Bridging for 10/100 ................................................................................................................ 12 2.7.2 Ethernet Traffic Classification .............................................................................................................. 12 2.7.3 Ethernet Bandwidth Policing ................................................................................................................ 12 2.7.4 Ethernet Traffic Scheduling.................................................................................................................. 12 2.7.5 Connection Endpoints.......................................................................................................................... 12 2.7.6 Virtual Connection................................................................................................................................ 12 2.7.7 Connection and Aggregation ............................................................................................................... 12 2.7.8 Ethernet Control Frame Processing..................................................................................................... 12 2.7.9 Q-in-Q .................................................................................................................................................. 12 2.8 SERIAL PORTS ..............................................................................................................................13 2.8.1 Voice Ports........................................................................................................................................... 13 2.9 MICROPROCESSOR INTERFACE......................................................................................................13 2.10 SLAVE SERIAL PERIPHERAL INTERFACE (SPI) FEATURES ............................................................13 2.11 TEST AND DIAGNOSTICS.............................................................................................................13 2.12 SPECIFICATIONS COMPLIANCE....................................................................................................13 3. APPLICABLE EQUIPMENT TYPES..............................................................................................14 4. ACRONYMS & GLOSSARY ..........................................................................................................17 5. DESIGNING WITH THE DS33X162 FAMILY OF DEVICES..........................................................18 5.1 IDENTIFICATION OF APPLICATION REQUIREMENTS ..........................................................................18 5.2 DEVICE SELECTION .......................................................................................................................18 5.3 ANCILLARY DEVICE SELECTION......................................................................................................19 5.4 CIRCUIT DESIGN............................................................................................................................19 5.5 BOARD LAYOUT.............................................................................................................................19 5.6 SOFTWARE DEVELOPMENT............................................................................................................19 6. BLOCK DIAGRAMS ......................................................................................................................20 7. PIN DESCRIPTIONS......................................................................................................................21 7.1 PIN FUNCTIONAL DESCRIPTION......................................................................................................21 8. FUNCTIONAL DESCRIPTION.......................................................................................................34 8.1 PARALLEL PROCESSOR INTERFACE................................................................................................35 8.1.1 Read-Write/Data Strobe Modes........................................................................................................... 35 8.1.2 Clear on Read...................................................................................................................................... 35 8.1.3 Interrupt and Pin Modes....................................................................................................................... 35 8.1.4 Multiplexed Bus Operation................................................................................................................... 35 8.2 SPI SERIAL PROCESSOR INTERFACE .............................................................................................36 8.3 CLOCK STRUCTURE.......................................................................................................................37 8.3.1 Serial Interface Clock Modes ............................................................................................................... 39 8.3.2 Ethernet Interface Clock Modes........................................................................................................... 39 Rev: 063008 2 of 375