Rev: 032609 DS34S101, DS34S102, DS34S104, DS34S108 Single/Dual/Quad/Octal TDM-over-Packet Chip General Description Features Transport of E1, T1, E3, T3 or STS-1 TDM or These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC Other CBR Signals Over Packet Networks compliant devices allow up to eight E1, T1 or serial streams or one high-speed E3, T3, STS-1 or serial Full Support for These Mapping Methods: stream to be transported transparently over IP, MPLS SAToP, CESoPSN, TDMoIP (AAL1), HDLC, or Ethernet networks. Jitter and wander of recovered Unstructured, Structured, Structured with CAS clocks conform to G.823/G.824, G.8261, and TDM Adaptive Clock Recovery, Common Clock, specifications. TDM data is transported in up to 64 External Clock and Loopback Timing Modes individually configurable bundles. All standards- On-Chip TDM Clock Recovery Machines, One based TDM-over-packet mapping methods are Per Port, Independently Configurable supported except AAL2. Frame-based serial HDLC Clock Recovery Algorithm Handles Network data flows are also supported. The high level of PDV, Packet Loss, Constant Delay Changes, integration available with the DS34S10x devices Frequency Changes and Other Impairments minimizes cost, board space, and time to market. 64 Independent Bundles/Connections Multiprotocol Encapsulation Supports IPv4, IPv6, UDP, RTP, L2TPv3, MPLS, Metro Ethernet Applications VLAN Support According to 802.1p and 802.1Q TDM Circuit Extension Over PSN 10/100 Ethernet MAC Supports MII/RMII/SSMII o Leased-Line Services Over PSN Selectable 32-Bit, 16-Bit or SPI Processor Bus o TDM Over GPON/EPON o TDM Over Cable Operates from Only Two Clock Signals, One for o TDM Over Wireless Clock Recovery and One for Packet Processing Cellular Backhaul Over PSN Glueless SDRAM Buffer Management Multiservice Over Unified PSN Low-Power 1.8V Core, 3.3V I/O HDLC-Based Traffic Transport Over PSN See detailed feature list in Section 7. Functional Diagram Ordering Information PART PORTS TEMP RANGE PIN-PACKAGE CPU Bus DS34S101GN 1 -40C to +85C 256 TECSBGA DS34S108 DS34S101GN+ 1 256 TECSBGA -40C to +85C DS34S102GN 2 -40C to +85C 256 TECSBGA Circuit 10/100 xMII TDM Emulation Ethernet DS34S102GN+ 2 256 TECSBGA Interface -40C to +85C Interfaces Engi ne MAC DS34S104GN 4 -40C to +85C 256 TECSBGA DS34S104GN+ 4 256 TECSBGA -40C to +85C Clock Buffer Manager Adapters DS34S108GN 8 -40C to +85C 484 HSBGA DS34S108GN+ 8 -40C to +85C 484 HSBGA SDRAM Clock Inputs +Denotes a lead(Pb)-free/RoHS-compliant package (explanation). Interface Maxim Integrated Products 1 Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxims website at www.maxim-ic.com. DS34S101, DS34S102, DS34S104, DS34S108 Table of Contents 1. INTRODUCTION ................................................................................................................................. 7 2. ACRONYMS AND GLOSSARY .......................................................................................................... 8 3. APPLICABLE STANDARDS ............................................................................................................ 10 4. DETAILED DESCRIPTION ............................................................................................................... 11 5. APPLICATION EXAMPLES .............................................................................................................. 12 6. BLOCK DIAGRAM ............................................................................................................................ 14 7. FEATURES ....................................................................................................................................... 15 8. OVERVIEW OF MAJOR OPERATIONAL MODES ........................................................................... 17 9. PIN DESCRIPTIONS ......................................................................................................................... 18 9.1 SHORT PIN DESCRIPTIONS.............................................................................................................. 18 9.2 DETAILED PIN DESCRIPTIONS ......................................................................................................... 20 10. FUNCTIONAL DESCRIPTION ........................................................................................................ 28 10.1 POWER-SUPPLY CONSIDERATIONS ............................................................................................... 28 10.2 CPU INTERFACE .......................................................................................................................... 28 10.3 SPI INTERFACE ............................................................................................................................ 31 10.3.1 SPI Operation .................................................................................................................................... 31 10.3.2 SPI Modes ......................................................................................................................................... 32 10.3.3 SPI Signals ........................................................................................................................................ 33 10.3.4 SPI Protocol ....................................................................................................................................... 33 10.4 CLOCK STRUCTURE ...................................................................................................................... 36 10.5 RESET AND POWER-DOWN ........................................................................................................... 37 10.6 TDM-OVER-PACKET BLOCK .......................................................................................................... 37 10.6.1 Packet Formats .................................................................................................................................. 37 10.6.2 Typical Application ............................................................................................................................. 47 10.6.3 Clock Recovery .................................................................................................................................. 48 10.6.4 Timeslot Assigner (TSA) ..................................................................................................................... 49 10.6.5 CAS Handler ...................................................................................................................................... 50 10.6.6 AAL1 Payload Type Machine ............................................................................................................. 54 10.6.7 HDLC Payload Type Machine............................................................................................................. 57 10.6.8 RAW Payload Type Machine .............................................................................................................. 58 10.6.9 SDRAM and SDRAM Controller ......................................................................................................... 62 10.6.10 Jitter Buffer Control (JBC) ................................................................................................................. 63 10.6.11 Queue Manager ............................................................................................................................... 66 10.6.12 Ethernet MAC................................................................................................................................... 78 10.6.13 Packet Classifier .............................................................................................................................. 81 10.6.14 Packet Trailer Support ...................................................................................................................... 84 10.6.15 Counters and Status Registers ......................................................................................................... 85 10.6.16 Connection Level Redundancy ......................................................................................................... 85 10.6.17 OAM Signaling ................................................................................................................................. 86 10.7 GLOBAL RESOURCES ................................................................................................................... 87 10.8 PER-PORT RESOURCES................................................................................................................ 87 10.9 DEVICE INTERRUPTS .................................................................................................................... 87 11. DEVICE REGISTERS...................................................................................................................... 89 11.1 ADDRESSING................................................................................................................................ 89 11.2 TOP-LEVEL MEMORY MAP ............................................................................................................ 90 Rev: 032609 2 of 198