19-4750 Rev 1 7/11 DS34S132 32-Port TDM-over-Packet IC General Description Features The IETF PWE3 SAToP/CESoPSN/HDLC-compliant 32 Independent TDM Ports with Serial Data, Clock, and Sync (Data = 64Kbps to 2.048Mbps) DS34S132 provides the interworking functions that are required for translating TDM data streams into One 100/1000Mbps (MII/GMII) Ethernet MAC and out of TDM-over-Packet (TDMoP) data streams 256 Total PWs, 32 PW per TDM Port, with Any for L2TPv3/IP, UDP/IP, MPLS (MFA-8), and Metro Combination of TDMoP and/or HDLC PWs Ethernet (MEF-8) networks while meeting the jitter PSN Protocols: L2TPv3 or UDP Over IP (IPv4 or and wander timing performance that is required by IPv6), Metro Ethernet (MEF-8), or MPLS (MFA-8) the public network (ITU G.823, G.824, and G.8261). Up to 32 TDM ports can be translated into as many 0, 1, or 2 VLAN Tags (IEEE 802.1Q) as 256 individually configurable pseudowires (PWs) Synchronous or Asynchronous TDM Port for transmission over a 100/1000Mbps Ethernet port. Timing Each TDM ports bit rate can vary from 64Kbps to One Clock Recovery Engine per TDM Port with 2.048Mbps to support T1/E1 or slower TDM rates. One Assignable as a Global Reference PW interworking for TDM-based serial HDLC data is Supported Clock Recovery Techniques also supported. A built-in time-slot assignment (TSA) Adaptive Clock Recovery circuit provides the ability to combine any group of Differential Clock Recovery time slots (TS) from a single TDM port into a single Absolute and Differential Timestamps PW. The high level of integration provides the perfect Independent Receive and Transmit Interfaces solution for high-density applications to minimize Two Clock Inputs for Direct Transmit Timing cost, board space, and time to market. For Structured T1/E1, Each TDM Port Includes DS0 TSA Block for any Time Slot to Any PW 32 HDLC/CES Engines (256 Total) Applications With or Without CAS Signaling TDM Circuit Emulation Over PSN For Unstructured, each TDM Port Includes TDM Leased-Line Services Over PSN One HDLC/SAT Engine (32 Total) TDM Over BPON/GPON/EPON Any data rate from 64Kbps to 2.048Mbps TDM Over Cable 32-Bit or 16-Bit CPU Processor Bus TDM Over Wireless CPU-Based OAM and Signaling Cellular Backhaul UDP-specific Special Ethernet Type Multiservice Over Unified PSN Inband VCCV ARP HDLC-Encapsulated Data Over PSN MEF OAM NDP/IPv6 Broadcast DA Functional Diagram CPU Interface DDR SDRAM Interface Low-Power 1.8V Core, 3.3V I/O, 2.5V SDRAM DS34S1328 32 TDM Ports Packet Circuit 100/1000 Ordering Information 32 Serial Generator Emulation MII/ Clock & Ethernet T1/E1 & HDLC GMII Data TSA Packet MAC PART PORTS TEMP RANGE PIN-PACKAGE Engines Interfaces Classifier DS34S132GNA2 32 676 BGA -40C to +85C BERT, CAS & Buffer Clock Conditioning Manager DS34S132GNA2+ 32 -40C to +85C 676 BGA Adapter +Denotes a lead(Pb)-free/RoHS-compliant package. Clock Inputs DDR SDRAM & Outputs Interface Maxim Integrated Products 1 Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxims website at www.maxim-ic.com. DS34S132 DATA SHEET TABLE OF CONTENTS 1 Introduction .................................................................................................................................................... 8 2 Acronyms and Glossary ................................................................................................................................. 9 3 Applicable Standards ................................................................................................................................... 10 4 High Level Description ................................................................................................................................. 11 5 Application Examples ................................................................................................................................... 13 6 Block Diagram ............................................................................................................................................. 15 7 Features ...................................................................................................................................................... 16 8 Pin Descriptions ........................................................................................................................................... 20 8.1 Short Pin Descriptions ........................................................................................................................... 20 8.2 Detailed Pin Descriptions ....................................................................................................................... 22 9 Functional Description .................................................................................................................................. 27 9.1 Connection Types .................................................................................................................................. 29 9.1.1 SAT/CES Payload Connections ..................................................................................................... 29 9.1.2 HDLC Connections ........................................................................................................................ 29 9.1.3 SAT/CES PW-Timing Connections ................................................................................................. 30 9.1.4 CPU Connections .......................................................................................................................... 31 9.2 TDM Port Functions ............................................................................................................................... 32 9.2.1 TDM Port Related Input and Output Clocks .................................................................................... 32 9.2.1.1 PW-Timing ............................................................................................................................. 33 9.2.1.1.1 RXP Clock Recovery (RXP PW-Timing) ......................................................................... 34 9.2.1.1.2 TXP PW-Timing ............................................................................................................. 34 9.2.1.2 TDM Port - One Clock and Two Clock Modes ......................................................................... 35 9.2.2 TDM Port Interface......................................................................................................................... 35 9.2.2.1 TDM Port Transmit Interface .................................................................................................. 36 9.2.2.2 TDM Port Receive Interface ................................................................................................... 37 9.2.3 TDM Port Structure & Frame Formats ............................................................................................ 37 9.2.4 Timeslot Assignment Block ............................................................................................................ 38 9.2.4.1 TDM CAS to Packet CAS Translation ..................................................................................... 40 9.2.4.2 TSA Block Loopbacks ............................................................................................................ 42 9.2.5 TDM Port Data Processing Engines ............................................................................................... 42 9.2.5.1 HDLC Engine ......................................................................................................................... 43 9.2.5.1.1 SAT/CES Engine ............................................................................................................ 44 9.2.5.2 TDM Port Priority.................................................................................................................... 45 9.2.5.3 Jitter Buffer Settings ............................................................................................................... 45 9.2.6 TDM Diagnostic Functions ............................................................................................................. 50 9.2.6.1 TDM Loopback ....................................................................................................................... 50 9.2.6.2 TDM BERT ............................................................................................................................ 51 9.3 Packet Processing Functions ................................................................................................................. 53 9.3.1 Ethernet MAC ................................................................................................................................ 53 9.3.1.1 Ethernet Port Diagnostic Functions ........................................................................................ 54 9.3.1.1.1 Ethernet Loopback ......................................................................................................... 54 9.3.1.1.2 Packet BERT ................................................................................................................. 54 9.3.2 RXP Packet Classification .............................................................................................................. 56 9.3.2.1 Generalized Packet Classification .......................................................................................... 56 9.3.2.2 PW (BID and OAM BID) Packet Classification ........................................................................ 57 9.3.2.2.1 UDP Settings ................................................................................................................. 58 9.3.2.2.2 Handling of Packets with a Matching BID or OAM BID .................................................... 58 9.3.2.2.3 L-bit Signaling for RXP PWs ........................................................................................... 59 9.3.2.3 CPU Packet Classification ...................................................................................................... 59 9.3.2.3.1 Packets with Broadcast Ethernet DA (DPC.CR1.DPBTP and DPC.CR1.DPBCP) ........... 60 9.3.2.3.2 Packets with Unknown Ethernet DA (PC.CR7 PC.CR19 and DPC.CR1.DPS9) ............ 60 9.3.2.3.3 PW Packets with Unknown PW-ID (DPS6) ..................................................................... 60 9.3.2.3.4 MEF OAM Ethernet Type Packets (MOET) ..................................................................... 60 9.3.2.3.5 CPU Destination Ethernet Type Packets (CDET and DPS8) ........................................... 60 9.3.2.3.6 ARP Packet with Known IP Destination Address (PC.CR6 PC.CR8 and DPS3) ........... 60 9.3.2.3.7 ARP Packet with Unknown IP Destination Address (PC.CR6 PC.CR8 and DPS0) ....... 60 9.3.2.3.8 Packet with Unknown Ethernet Type (DPS2) .................................................................. 60 19-4750 Rev1 7/11 2 of 194