19-4835 8/09 DS34T101, DS34T102, DS34T104, DS34T108 Single/Dual/Quad/Octal TDM-over-Packet Chip General Description Features Full-Featured IC Includes E1/T1 LIUs and These IETF PWE3 SAToP/CESoPSN/TDMoIP/HDLC Framers, TDMoP Engine, and 10/100 MAC compliant devices allow up to eight E1, T1 or serial streams or one high-speed E3, T3, STS-1 or serial Transport of E1, T1, E3, T3 or STS-1 TDM or stream to be transported transparently over IP, MPLS Other CBR Signals Over Packet Networks or Ethernet networks. Jitter and wander of recovered Full Support for These Mapping Methods: clocks conform to G.823/G.824, G.8261, and TDM SAToP, CESoPSN, TDMoIP AAL1, HDLC, specifications. TDM data is transported in up to 64 Unstructured, Structured, Structured with CAS individually configurable bundles. All standards- Adaptive Clock Recovery, Common Clock, based TDM-over-packet mapping methods are External Clock and Loopback Timing Modes supported except AAL2. Frame-based serial HDLC On-Chip TDM Clock Recovery Machines, One data flows are also supported. With built-in full- Per Port, Independently Configurable featured E1/T1 framers and LIUs. These ICs encapsulate the TDM-over-packet solution from Clock Recovery Algorithm Handles Network analog E1/T1 signal to Ethernet MII while preserving PDV, Packet Loss, Constant Delay Changes, options to make use of TDM streams at key Frequency Changes and Other Impairments intermediate points. The high level of integration 64 Independent Bundles/Connections available with the DS34T10x devices minimizes cost, Multiprotocol Encapsulation Supports IPv4, board space, and time to market. IPv6, UDP, RTP, L2TPv3, MPLS, Metro Ethernet VLAN Support According to 802.1p and 802.1Q Applications 10/100 Ethernet MAC Supports MII/RMII/SSMII TDM Circuit Extension Over PSN Selectable 32-Bit, 16-Bit or SPI Processor Bus o Leased-Line Services Over PSN Operates from Only Two Clock Signals, One for o TDM Over GPON/EPON Clock Recovery and One for Packet Processing o TDM Over Cable Glueless SDRAM Buffer Management o TDM Over Wireless Cellular Backhaul Over PSN Low-Power 1.8V Core, 3.3V I/O Multiservice Over Unified PSN See detailed feature list in Section 7. HDLC-Based Traffic Transport Over PSN Ordering Information Functional Diagram PART PORTSTEMP RANGE PIN-PACKAGE CPU Bus DS34T101GN 1 484 TEBGA -40C to +85C DS34T108 DS34T101GN+ 1 -40C to +85C 484 TEBGA Octal Circuit DS34T102GN 2 484 TEBGA E1/T1/J1 10/100 -40C to +85C Emulation Transceiver Ethernet DS34T102GN+ 2 -40C to +85C 484 TEBGA Engine xMII MAC Framers DS34T104GN 4 484 TEBGA -40C to +85C E1/T1 BERT & CAS Interfaces DS34T104GN+ 4 -40C to +85C 484 TEBGA Clock Buffer LIUs Manager Adapters DS34T108GN 8 484 HSBGA -40C to +85C DS34T108GN+ 8 -40C to +85C 484 HSBGA TDM SDRAM Clock Inputs +Denotes lead(Pb)-free/RoHS-compliant package (explanation). Access Interface Maxim Integrated Products 1 Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxims website at www.maxim-ic.com. DS34T101, DS34T102, DS34T104, DS34T108 Table of Contents 1 INTRODUCTION ...................................................................................................................................10 2 ACRONYMS AND GLOSSARY............................................................................................................10 3 APPLICABLE STANDARDS ................................................................................................................13 4 DETAILED DESCRIPTION ...................................................................................................................14 5 APPLICATION EXAMPLES .................................................................................................................16 6 BLOCK DIAGRAM................................................................................................................................18 7 FEATURES ...........................................................................................................................................20 8 OVERVIEW OF MAJOR OPERATIONAL MODES..............................................................................25 8.1 INTERNAL MODE................................................................................................................................25 8.1.1 Internal One-Clock Mode........................................................................................................................... 26 8.1.2 Internal Two-Clock Mode........................................................................................................................... 26 8.2 EXTERNAL MODE ..............................................................................................................................27 9 PIN DESCRIPTIONS.............................................................................................................................28 9.1 SHORT PIN DESCRIPTIONS ................................................................................................................28 9.2 DETAILED PIN DESCRIPTIONS ............................................................................................................30 10 FUNCTIONAL DESCRIPTION............................................................................................................44 10.1 POWER-SUPPLY CONSIDERATIONS..................................................................................................44 10.2 CPU INTERFACE .............................................................................................................................44 10.3 SPI INTERFACE ...............................................................................................................................47 10.3.1 SPI Operation .......................................................................................................................................... 47 10.3.2 SPI Modes ............................................................................................................................................... 48 10.3.3 SPI Signals .............................................................................................................................................. 49 10.3.4 SPI Protocol............................................................................................................................................. 49 10.4 CLOCK STRUCTURE.........................................................................................................................52 10.5 RESET AND POWER-DOWN..............................................................................................................53 10.6 TDM-OVER-PACKET BLOCK.............................................................................................................54 10.6.1 Packet Formats ....................................................................................................................................... 54 10.6.2 Typical Application................................................................................................................................... 63 10.6.3 Clock Recovery ....................................................................................................................................... 65 10.6.4 Timeslot Assigner (TSA).......................................................................................................................... 66 10.6.5 CAS Handler............................................................................................................................................ 67 10.6.6 AAL1 Payload Type Machine .................................................................................................................. 71 10.6.7 HDLC Payload Type Machine ................................................................................................................. 74 10.6.8 RAW Payload Type Machine .................................................................................................................. 75 10.6.9 SDRAM and SDRAM Controller.............................................................................................................. 79 10.6.10 Jitter Buffer Control (JBC) ..................................................................................................................... 80 10.6.11 Queue Manager..................................................................................................................................... 83 10.6.12 Ethernet MAC ........................................................................................................................................ 95 10.6.13 Packet Classifier.................................................................................................................................... 98 10.6.14 Packet Trailer Support......................................................................................................................... 101 10.6.15 Counters and Status Registers ........................................................................................................... 102 10.6.16 Connection Level Redundancy ........................................................................................................... 102 10.6.17 OAM Signaling..................................................................................................................................... 103 10.7 GLOBAL RESOURCES ....................................................................................................................104 10.8 PER-PORT RESOURCES ................................................................................................................104 10.9 DEVICE INTERRUPTS .....................................................................................................................104 2 of 366