EVALUATION KIT AVAILABLE DS3922 High-Speed Current Mirror and Integrated FETs for DC-DC Controller General Description Benefits and Features The DS3922 high-speed current mirror integrates high- Accurate Burst-Mode RSSI Measurement with Two voltage devices necessary for monitoring the burst mode Current Mirror Outputs Improves Dynamic Range receive power signal in avalanche photodiode (APD) bias- -32dBm to -5dBm Optical Input Range ing and OLT applications. The device has two small and 0.5dB Accuracy one large gain current mirror outputs to monitor the APD Sampling Period as Short as 300ns current. An adjustable current clamp limits current through Pin Discharge Option the APD. The clamp also features an external shutdown. An integrated FET is also provided that can be used to Low-Noise APD Bias with Shutdown Options quickly clamp the high-voltage bias to ground in the case Reduces Receiver Sensitivity of high optical input power. Integrated low-voltage FET 15V to 76V APD Bias circuits can be used to create buck, boost, and inverting External Capacitor Connection for Controlled RC DC-DC converters for efficient laser bias and EML bias Time Constant of APD Voltage Filter applications. Current Clamp with Adjustable Limit and External The DS3922 is available in a 24-pin TQFN package and Shutdown with Limit Status operates over an extended -40C to +95C temperature High-Voltage Switch FET for APD Fast Shutdown range. Supports Additional DC-DC Functions Low-Voltage Synchronous Buck FETs for Efficient Block Diagram DFB Bias Low-Voltage pMOSFET for Generating Negative Bias Voltage for EMLs LOW-VOLTAGE V DS3922 CC FET CIRCUITS Small Package Reduces Total Solution Size and Cost LVCC AVCC (2.85V TO 3.63V) 3.5mm x 3.5mm, 24-Pin TQFN Package with (WITHIN 0.1V OF MIRIN HIGH-VOLTAGE HVGND AND GND) AND MIRROR CIRCUITS Exposed Pad LVGND I1 AVCC 4V 0.8I1 0.2I1 0.1I1 Applications Avalanche Photodiode (APD ) Monitoring MIRCAP HIGH-POWER DML, DFB, LDD, TXVCC LVOUT3 GPON OLT LVCC (0 TO 4V) OPEN-DRAIN nMOS 10GPON OLT ILIMS CURRENT RLIM LIMIT EML Bias LVGND LVGND LVIN3 200A 10G EPON TEMP EML NEGATIVE BIAS INVERTING SWITCHER LVIN2 LIMIT LVCC LVCC ISRC/SHDN Ordering Information appears at end of data sheet. pMOS 1.8V LVOUT2 AVCC LVGND MIROUT (-3.7V TO LVCC) MIRIN OPEN-DRAIN pMOS APDV 0.5V/V For related parts and recommended products to use with this part, refer EML, DFB, APC HIGH-EFFICIENCY BIAS LVIN1 MIROUT to www.maximintegrated.com/DS3922.related. GND LVCC LVCC HVD pMOS HVGND LVOUT1 NONOVERLAP V CC (0 TO LVCC) DRIVER HVG nMOS LVGND LVGND 19-7400 Rev 1 3/15 IOUT VIP1 VIP2DS3922 High-Speed Current Mirror and Integrated FETs for DC-DC Controller Absolute Maximum Ratings Voltage on HVD, MIRIN, MIRCAP, and Voltage on All Other Pins MIROUT Relative to HVGND ............................-0.3V to +79V Relative to GND ........-0.3V to (V + 0.3V) not to exceed +4V CC Voltage on MIROUT Relative to HVGND ...-0.3V to (V + 0.3V) Continuous Power Dissipation (T = +70C) MIRIN A Voltage on LVOUT1 Relative TQFN (derate 15.4mW/C above +70C)...............1228.9mW to LVGND ..........................................-0.3V to (V + 0.3V) Storage Temperature Range ............................ -55C to +135C LVCC Voltage on LVOUT2 Relative to LVGND ..-4V to (V + 0.3V) Lead Temperature (soldering, 10s) .................................+300C LVCC Voltage on LVOUT3 Relative to LVGND .................-0.3V to +5V Soldering Temperature, Lead(Pb)-Free Reflow ...............+260C Voltage on LVCC Relative to V ......................................0.1V CC Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Thermal Characteristics (Note 1) TQFN Junction-to-Ambient Thermal Resistance ( ) .........5.4C/W JA Junction-to-Case Thermal Resistance ( ) ............65.1C/W JC Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-lay- er board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. Electrical Characteristics (V = 15V to 76V, V = 2.85V to 3.63V, T = -40C to +95C, unless otherwise noted.) (Note 2) MIRIN CC A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Low-Voltage Supply V 2.85 3.63 V CC Low-Voltage Current I (Note 3) 1.5 3.0 mA CC V = 60V, MIRIN I = 0A 1 2 MIROUT MIRIN Quiescent Current I ISRC/SHDN = 30k mA MIRIN I = 1mA 3.2 4.5 to GND MIROUT MIRIN Voltage V 15 76 V MIRIN V falling from 90% to 10% of peak DHV HV FET Turn-On Time t 30 ns ON:HV voltage HV FET On-Resistance R V = 3.0V, I = 170mA 0.85 2 DSONHV GS D V + CC HVG Voltage V 0 V GSHV 0.3 HVD Voltage V 76 V DHV HVD Leakage I -1 +1 A ILHV 0.25 x V IL V CC Logic Input Thresholds: HVG, V LVIN1, LVIN2, LVIN3 0.65 x V IH V CC V 1.4 IL SHDN Note: Compatible with 2.5V and 3.3V ISRC/SHDN Threshold V V - CC CMOS logic levels V IH SHDN 0.2 ISRC/SHDN Resistor R (Note 4) 29.7 30 30.3 k ISRC Maxim Integrated 2 www.maximintegrated.com