DS4M125/DS4M133/DS4M200 Rev 0 12/07 3.3V Margining Clock Oscillator with LVPECL/LVDS Output General Description Features The DS4M125/DS4M133/DS4M200 are margining clock Frequency Margining: 5% oscillators with LVPECL or LVDS outputs. They are Nominal Clock Output Frequencies: 125MHz, designed to fit in a 5mm x 3.2mm ceramic package with 133.33MHz, and 200MHz an AT-cut fundamental-mode crystal to form a complete clock oscillator. The circuit can generate the following Jitter < 0.9ps RMS from 12kHz to 20MHz frequencies and their 5% frequency deviations: LVPECL or LVDS Output 125MHz, 133.33MHz, and 200MHz. The DS4M125/ DS4M133/DS4M200 employ a low-jitter PLL to generate 3.3V Operating Voltage the frequencies. The typical phase jitter is less than Operating Temperature Range: -40C to +85C 0.9ps RMS from 12kHz to 20MHz. Frequency margining is a circuit operation to change Supply Current: < 100mA at 3.3V the output frequency to 5% higher or 5% lower than the Excellent Power-Supply Noise Rejection nominal frequency. Frequency margining is accom- plished through the margining select pin, MS. This 5mm x 3.2mm Ceramic LCCC Package three-state input pin accepts a three-level voltage signal Output Enable/Disable to control the output frequency. In a low-level state, the output frequency is set to the nominal frequency. When set to a high-level state, the frequency output is set to Ordering Information the nominal frequency plus 5%. When set to the mid- PART TEMP RANGE PIN-PACKAGE level state, the frequency output is equal to the nominal frequency minus 5%. If left open, the MS pin is pulled DS4M125P+33 -40C to +85C 10 LCCC low by an internal 100k (nominal) pulldown resistor. DS4M125D+33 -40C to +85C 10 LCCC The DS4M125/DS4M133/DS4M200 are available with DS4M133P+33 -40C to +85C 10 LCCC either an LVPECL or LVDS output. The output can be DS4M133D+33 -40C to +85C 10 LCCC disabled by pulling the OE pin low. When disabled, DS4M200P+33 -40C to +85C 10 LCCC both OUTP and OUTN levels of the LVPECL driver go to DS4M200D+33 -40C to +85C 10 LCCC the LVPECL bias voltage, while the output of the LVDS driver is a logical one. The OE input is an active-high +Denotes a lead(Pb)-free package. The lead finish is JESD97 logic signal and has an internal 100k pullup resistor. category e4 (Au over Ni) and is compatible with both lead-based When OE is in a logic-high state, the OUTP and OUTN and lead-free soldering processes. outputs are enabled. The devices operate from a single 3.3V supply voltage. Pin Configuration and Selector Guide appear at end of Applications data sheet. Memory Clocks RAID Systems Typical Operating Circuit VCC OUTP VCC OUTP 0.1F 0.01F 0.1F 0.01F 50 DS4M125/ DS4M125/ PECL BIAS AT 100 MS MS V - 2.0V DS4M133/ DS4M133/ CC 50 DS4M200 DS4M200 OE OE GND OUTN GND OUTN LVDS OPTION LVPECL OPTION Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxims website at www.maxim-ic.com.3.3V Margining Clock Oscillator with LVPECL/LVDS Output ABSOLUTE MAXIMUM RATINGS Power-Supply Voltage Range (V ) .....................-0.3V to +4.0V Storage Temperature Range ...............................-55C to +85C CC Continuous Power Dissipation (T = +70C) ...................330mW Soldering Temperature A Operating Temperature Range ...........................-40C to +85C (3 passes max of reflow)..........................................Refer to the Junction Temperature......................................................+125C IPC/JEDEC J-STD-020 Specification. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (V = 3.135V to 3.465V, T = -40C to +85C, unless otherwise noted.) (Notes 1, 2) CC A PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Operating Voltage Range V (Note 1) 3.135 3.3 3.465 V CC I LVDS, output loaded or unloaded 52 75 CC D Operating Current mA I LVPECL, output unloaded 49 70 CC PU I LVPECL, output loaded 74 100 CC PI Inactive Current I V = V 52 85 mA CC OEZ OE IL OUTPUT FREQUENCY SPECIFICATIONS DS4M125 MS = 0, OE = 1 125 Frequency f MHz DS4M133 O MS = 0, OE = 1 133.33 DS4M200 MS = 0, OE = 1 200 Over temperature range, aging, load, Frequency Stability f f -50 +50 ppm TOTAL/ O supply, and initial tolerance (Note 3) Frequency Stability Over f /f V = 3.3V -35 +35 ppm TEMP CC Temperature Initial Tolerance f /f V = 3.3V, T = +25C 20 ppm INITIAL V CC A Frequency Change Due to V f /f V = 3.3V 5% -3 +3 ppm/V CC VCC CC Frequency Change Due to Load 10% variation in termination f f 1 ppm LOAD/ O Variation resistance Aging (15 Years) f -7 +7 ppm AGING Integrated phase RMS 12kHz to 80MHz, Phase Jitter J < 0.9 ps RMS V = 3.3V, T = +25C CC A Accumulated Deterministic Jitter No margin 155.52MHz output 0.6 ps Due to Reference Spurs 10kHz 12.9 100kHz (Note 4) 26.3 Accumulated Deterministic Jitter ps Due to Power-Supply Noise 200kHz (Note 4) 20.1 1MHz (Note 4) 6.4 Startup Time t 1.0 ms STRT Frequency Switch Time t 0.5 ms SWITCH 0.7 x Input-Voltage High (OE) V (Note 5) V V IH CC V CC 2 DS4M125/DS4M133/DS4M200