DS5001FP 128k Soft Microprocessor Chip www.maxim-ic.com FEATURES PIN CONFIGURATIONS 8051-Compatible Microprocessor Adapts to Its TOP VIEW Task Accesses up to 128kB of nonvolatile SRAM In-system programming through on-chip serial port 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 Can modify its own program or data memory P0.4AD4 1 64 P2.6/A14 CE2 2 63 CE3 Accesses memory on a separate byte-wide bus PE2 3 62 CE4 BA9 4 61 BD3 Performs CRC-16 check of NV RAM P0.3/AD3 5 60 P2.5/A13 memory BA8 6 59 BD2 P0.2/AD2 7 58 P2.4/A12 Decodes memory and peripheral chip enables BA13 8 57 BD1 P0.1/AD1 9 56 P2.3/A11 High-Reliability Operation R/W 10 55 BD0 DS5001FP P0.0/AD0 11 54 VLI Maintains all nonvolatile resources for over VCC0 12 53 BA15 VCC 13 52 GND 10 years MSEL 14 51 P2.2/A10 Power-fail reset P1.0 15 50 P2.1/A9 49 P2.0/A8 BA14 16 Early warning power-fail interrupt P1.1 17 48 XTAL1 47 XTAL2 BA12 18 Watchdog timer P1.2 19 46 P3.7/RD BA7 20 45 P3.6/WR Lithium backs user SRAM for program/data P1.3 21 44 P3.5/TI PE3 22 43 PF storage PE4 23 42 VRST Precision bandgap reference for power BA6 24 41 P3.4/T0 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 monitor Fully 8051 Compatible 128kB scratchpad RAM Two timer/counters On-chip serial port MQFP 32 parallel I/O port pins Software Security Available with DS5002FP Secure Microprocessor This data sheet must be used in conjunction with the Secure Microcontroller Users Guide, available on our website at www.maxim-ic.com/microcontrollers. The users guide contains operating information, whereas the data sheet contains ordering information, pinout, and electrical specifications MQFP Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata. 1 of 27 REV: 070605 P1.4 BA11 BA5 P0.5/AD5 P1.5 PE1 BA4 P0.6/AD6 P1.6 BA10 BA3 P0.7/AD7 P1.7 CE1 PROG N.C. BA2 CE1N RST BD7 BA1 ALE P3.0/RXD BD6 BA0 PSEN P3.1/TXD BD5 P3.2/INT0 P2.7/A15 P3.3/INT1 BD4 DS5001FP ORDERING INFORMATION MAX CLOCK PIN- PART TEMP RANGE SPEED (MHz) PACKAGE DS5001FP-16 0C to +70C 16 80 MQFP DS5001FP-16+ 0C to +70C 16 80 MQFP DS5001FP-16N -40C to +85C 16 80 MQFP DS5001FP-16N+ -40C to +85C 16 80 MQFP DS5001FP-12-44 0C to +70C 12 44MQFP DS5001FP-12-44+ 0C to +70C 12 44 MQFP + Denotes a Pb-free/RoHS-compliant device. DESCRIPTION The DS5001FP 128k soft microprocessor chip is an 8051-compatible microprocessor based on NV RAM technology and designed for systems that need large quantities of nonvolatile memory. It provides full compatibility with the 8051 instruction set, timers, serial port, and parallel I/O ports. By using NV RAM instead of ROM, the user can program and then reprogram the microprocessor while in-system. The application software can even change its own operation, which allows frequent software upgrades, adaptive programs, customized systems, etc. In addition, by using NV SRAM, the DS5001FP is ideal for data logging applications. It also connects easily to a Dallas real-time clock. The DS5001FP provides the benefits of NV RAM without using I/O resources. It uses a nonmultiplexed byte-wide address and data bus for memory access. This bus performs all memory access and provides decoded chip enables for SRAM, which leaves the 32 I/O port pins free for application use. The DS5001FP uses ordinary SRAM and battery-backs the memory contents for over 10 years at room temperature with a small external battery. A DS5001FP also provides high-reliability operation in harsh environments. These features include the ability to save the operating state, power-fail reset, power-fail interrupt, and watchdog timer. A user programs the DS5001FP through its on-chip serial bootstrap loader. The bootstrap loader supervises the loading of software into NV RAM, validates it, and then becomes transparent to the user. Software can be stored in multiple 32kB or one 128kB CMOS SRAM(s). Using its internal partitioning, the DS5001FP can divide a common RAM into user-selectable program and data segments. This partition can be selected at program loading time, but can then be modified later at any time. The microprocessor decodes memory access to the SRAM and addresses memory through its byte-wide bus. Memory portions designated code or ROM are automatically write-protected by the microprocessor. Combining program and data storage in one device saves board space and cost. The DS5001FP offers several bank switches for access to even more memory. In addition to the primary data area of 64kB, a peripheral selector creates a second 64kB data space with four accompanying chip enables. This area can be used for memory-mapped peripherals or more data storage. The DS5001FP can also use its expanded bus on ports 0 and 2 (like an 8051) to access an additional 64kB of data space. Lastly, the DS5001FP provides one additional bank switch that changes up to 60kB of the NV RAM program space into data memory. Thus, with a small amount of logic, the DS5001 accesses up to 252kB of data memory. The DS2251T is available (Refer to the data sheet at www.maxim-ic.com/microcontrollers.) for users who want a preconstructed module using the DS5001FP, RAM, lithium cell, and a real-time clock. For more details, refer to the Secure Microcontroller Users Guide. For users desiring software security, the DS5002FP is functionally identical to the DS5001FP but provides superior firmware security. The 44-pin version of the device is functionally identical to the 80-pin version but sports a reduced pin count and footprint. 2 of 27