HMC988LP3E v04.1014 PROGRAMMABLE CLOCK DIVIDER AND DELAY DC - 4 GHz Typical Applications Features DC - 4 GHz t he HMC988l P3E is ideal for: -170 dbc/Hz floor 100 MHz output basestation Digital Pre-Distortion Paths(DPD) -164 dbc/Hz floor 2 GHz output High Performance Automated t est Equipment(At E) integrated Jitter 35 fs 100 MHz output r Ms 13 fs (calculated) 2 GHz output backplane clock skew management r Ms Adjustable output phase with soft/hard reset sync Phase Coherence of multiple clock paths Adjustable output delay in 60 steps of 20 ps Clock Delay management to improve setup & hold time margins Flexible input interface: PCb signal flight time offset circuits l VPECl ,l VDs ,CMl ,CMos Compatible AC or DC Coupling t rack and hold circuits for ADC/DACs o n - Chip t ermination 50 (100 Differential) o utput Driver (l VPECl ): 800 mVpp l VPECl into 50 s ingle-Ended (+3 Functional Diagram dbm Fo) u p to 8 addressable dividers per s Pi bus 3.3 V operation or 5 V operation with o ptional on- chip regulator for best performance 3 x 3 QFn l eadless s Mt Package General Description t he HMC988l P3E is a an ultra low noise clock divider capable of dividing by 1/2/4/8/16/32. it is a versatile device with additional functionality including adjustable output phase, adjustable delay in 60 steps of ~ 20 ps, a clock synchronization function, and a clock invert option. Housed in a compact 3x3 mm s Mt QFn package, the clock divider offers a high level of functionality. t he device works with 3.3 V supply or may be connected to 5 V supply and utilize the optional on-chip regulator. t his on-chip regulator may be bypassed. up to 8 addressable HMC988l P3E devices can be used together on the s Pi bus. t he HMC988l P3E is ideally suited for data converter applications with extremely low phase noise requirements. Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, delivery, and to place orders: Analog Devices, Inc., For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Phone: 781-329-4700 Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 1 Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 1-800-ANALOG-D Application Support: Phone: 978-250-3343 or apps hittite.com Clo Ck Distribution - s MtHMC988LP3E v04.1014 PROGRAMMABLE CLOCK DIVIDER AND DELAY DC - 4 GHz Table 1. Electrical Specifications u nless otherwise specified: t = +25 C. Current consumptions assumes fine adjustable delay is disabled. Phase noise degrades approximately 15 db if using fine delay adjustment. Parameter Conditions Min t yp. Max u nits os CP/n input Frequency r ange DC 4 GHz DiVP/n o utput Frequency r ange DC 4 GHz Divide r atios 1/2/4/8/16/32 Maximum Fine Delay Adjust Frequency DC 1 GHz VDD with on-chip regulator +3.7 +4.5 +5.5 V VDD bypass on-chip regulator +3.1 +3.3 +3.5 V 0.800 input s wing (l VPECl or AC) Vpp s ee Figure 9 Measured into a 50ohm 0.8 (single ended) Vpp l oad o utput s wing (l VPECl ) 1 Measured into a 50ohm 1.6 (differential) Vppd l oad r ise/Fall t ime (l VPECl ou t ) 20%/80% 90 ps os CP/n input Commom Mode DC bias 2 +1.6 +2 +2.5 V DiVP/n o utput Common Mode Voltage 1 +2 V Phase n oise ( 100 MHz offset) 3 100 MHz output -170 500 MHz output dbc/Hz -168 1 GHz output -166 2 GHz output -164 Jitter Density 4 100 MHz output 7.1 500 MHz output 1.8 asec/Hz 1 GHz output 1.1 2 GHz output 0.7 integrated Jitter (12k - 20MHz) 5 100 MHz output 32 500 MHz output 6 8 fsec 1 GHz output 6 5 2 GHz output 6 3.2 n oise Floor = Fo M (Figure of Merit) n oise Floor -254 dbc/Hz Fo M+10l og(Fout) input Coarse Delay Adjustment r ange 1/2 to *t in Pu t Cycles 60 steps of ~ 20 ps Delay compresses with increasing frequency. Fine Delay Adjustment r ange 7 s ee Figure 6. With 300 1500 ps divider bypassed maxi- mum frequency limited to 650MHz Fine Delay Adjustment r esolution 20 ps Fine Delay Adjustment s tep Count 60 Psrr 8 AM -70 -80 dbc With r egulator PM -80 -92 dbc Information furnished by Analog Devices is believed to be accurate and reliable. However, no For price, delivery, and to place orders: Analog Devices, Inc., For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824 responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 rights of third parties that may result from its use. Specifications subject to change without notice. No Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com Phone: 781-329-4700 Order online at www.analog.com license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 2 Trademarks and registered trademarks are the property of their respective owners. Application Support: Phone: 1-800-ANALOG-D Application Support: Phone: 978-250-3343 or apps hittite.com Clo Ck Distribution - s Mt