a 200 MHz Clock Generator PLL ADF4001 FEATURES GENERAL DESCRIPTION 200 MHz Bandwidth The ADF4001 clock generator can be used to implement clock 2.7 V to 5.5 V Power Supply sources for PLLs that require very low noise, stable reference Separate Charge Pump Supply (V ) Allows Extended signals. It consists of a low noise digital PFD (phase frequency P Tuning Voltage in 5 V Systems detector), a precision charge pump, a programmable reference Programmable Charge Pump Currents divider, and a programmable 13-bit N counter. In addition, the 3-Wire Serial Interface 14-bit reference counter (R counter) allows selectable REF IN Hardware and Software Power-Down Mode frequencies at the PFD input. A complete PLL (phase-locked Analog and Digital Lock Detect loop) can be implemented if the synthesizer is used with an exter- Hardware Compatible to the ADF4110/ADF4111/ nal loop filter and VCO (voltage controlled oscillator) or ADF4112/ADF4113 VCXO (voltage controlled crystal oscillator). The N minimum Typical Operating Current 4.5 mA value of 1 allows flexibility in clock generation. Ultralow Phase Noise 16-Lead TSSOP 20-Lead LFCSP APPLICATIONS Clock Generation Low Frequency PLLs Low Jitter Clock Source Clock Smoothing Frequency Translation SONET, ATM, ADM, DSLAM, SDM FUNCTIONAL BLOCK DIAGRAM AV DV V CPGND R DD DD P SET REFERENCE ADF4001 14-BIT REF IN R COUNTER PHASE FREQUENCY CP CHARGE DETECTOR PUMP 14 R COUNTER LATCH CURRENT CURRENT CLK LOCK DETECT SETTING 2 SETTING 1 24-BIT FUNCTION DATA INPUT REGISTER LATCH 22 LE CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 SD OUT N COUNTER LATCH HIGH Z AV DD 13 MUXOUT MUX RF A IN 13-BIT SD OUT N COUNTER RF B IN M1 M3 M2 CE AGND DGND REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Trademarks and Fax: 781/461-3113 2013 Analog Devices, Inc. All rights reserved. registered trademarks are the property of their respective owners.1 ADF4001SPECIFICATIONS (AV = DV = 3 V 10%, 5 V 10% AV V 6.0 V AGND = DGND = DD DD DD P CPGND = 0 V R = 4.7 k T = T to T , unless otherwise noted dBm referred to 50 .) SET A MIN MAX Parameter B Version Unit Test Conditions/Comments RF CHARACTERISTICS (3 V) See Figure 3 for Input Circuit RF Input Frequency 5/165 MHz min/max RF Input Sensitivity 10/0 dBm min/max RF CHARACTERISTICS (5 V) RF Input Frequency 10/200 MHz min/max 5/0 dBm min/max 20/200 MHz min/max 10/0 dBm min/max REF CHARACTERISTICS See Figure 2 for Input Circuit IN REF Input Frequency 5/104 MHz min/max For f < 5 MHz, Use DC-Coupled Square Wave IN (0 to V ) DD 2 REF Input Sensitivity 5 dBm min AC-Coupled. When DC-Coupled: IN 0 to V Max (CMOS Compatible) DD REF Input Capacitance 10 pF max IN REF Input Current 100 A max IN PHASE DETECTOR 3 Phase Detector Frequency 55 MHz max CHARGE PUMP I Sink/Source Programmable: See Table V CP High Value 5 mA typ With R = 4.7 k SET Low Value 625 A typ Absolute Accuracy 2.5 % typ With R = 4.7 k SET R Range 2.7/10 k typ See Table V SET I Three-State Leakage Current 1 nA typ CP Sink and Source Current Matching 2 % typ 0.5 V V V 0.5 CP P I vs. V 1.5 % typ 0.5 V V V 0.5 CP CP CP P I vs. Temperature 2 % typ V = V /2 CP CP P LOGIC INPUTS V , Input High Voltage 0.8 DV V min INH DD V , Input Low Voltage 0.2 DV V max INL DD I /I , Input Current 1 A max INH INL C , Input Capacitance 10 pF max IN LOGIC OUTPUTS V , Output High Voltage DV 0.4 V min I = 500 A OH DD OH V , Output Low Voltage 0.4 V max I = 500 A OL OL POWER SUPPLIES AV 2.7/5.5 V min/V max DD DV AV DD DD V AV /6.0 V min/V max AV V 6.0 V P DD DD P 4 I (AI + DI ) DD DD DD ADF4001 5.5 mA max 4.5 mA typical I 0.4 mA max T = 25C P A Low Power Sleep Mode 1 A typ NOISE CHARACTERISTICS 5 ADF4001 Phase Noise Floor 161 dBc/Hz typ 200 kHz PFD Frequency 153 dBc/Hz typ 1 MHz PFD Frequency 6 Phase Noise Performance VCXO Output 7 200 MHz Output 99 dBc/Hz typ 1 kHz Offset and 200 kHz PFD Frequency Spurious Signals 7 200 MHz Output 90/95 dBc typ/dBc typ 200 kHz/400 kHz and 200 kHz PFD Frequency NOTES 1 Operating temperature range (B Version) is 40C to +85C. 2 AV = DV = 3 V for AV = DV = 5 V, use CMOS compatible levels. DD DD DD DD 3 Guaranteed by design. Sample tested to ensure compliance. 4 T = 25C AV = DV = 3 V RF = 100 MHz. A DD DD IN 5 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value). 6 The phase noise is measured with the EVAL-ADF4001EB1 evaluation board and the HP8562E spectrum analyzer. 7 f = 10 MHz f = 200 kHz Offset Frequency = 1 kHz f = 200 MHz N = 1000 Loop B/W = 20 kHz. REF PFD RF IN Specifications subject to change without notice. 2 REV. B