X-On Electronics has gained recognition as a prominent supplier of EV-ADF4113HVSD1Z Clock & Timer Development Tools across the USA, India, Europe, Australia, and various other global locations. EV-ADF4113HVSD1Z Clock & Timer Development Tools are a product manufactured by Analog Devices. We provide cost-effective solutions for Clock & Timer Development Tools, ensuring timely deliveries around the world.

EV-ADF4113HVSD1Z Analog Devices

EV-ADF4113HVSD1Z electronic component of Analog Devices
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Part No.EV-ADF4113HVSD1Z
Manufacturer: Analog Devices
Category: Clock & Timer Development Tools
Description: Analog Devices Clock & Timer Development Tools EVAL BRD ADF4113HV
Datasheet: EV-ADF4113HVSD1Z Datasheet (PDF)
This product is classified as Large/Heavy, additional shipping charges may apply. A customer service representative may contact you after ordering to confirm exact shipping charges



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High Voltage Charge Pump, PLL Synthesizer Data Sheet ADF4113HV FEATURES GENERAL DESCRIPTION High voltage charge pump (15 V) The ADF4113HV is an integer-N frequency synthesizer with a 2.7 V to 5.5 V power supply high voltage charge pump (15 V). The synthesizer is designed 200 MHz to 4.0 GHz frequency range for use with voltage controlled oscillators (VCOs) that have Pin compatible with ADF4110, ADF4111, ADF4112, ADF4113 high tuning voltages (up to 15 V). Active loop filters are often ADF4106, and ADF4002 synthesizers used to achieve high tuning voltages, but the ADF4113HV Two selectable charge pump currents charge pump can drive a high voltage VCO directly with a Digital lock detect passive-loop filter. The ADF4113HV can be used to implement Power-down mode local oscillators in the upconversion and downconversion Loop filter design possible with ADIsimPLL sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision APPLICATIONS high voltage charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler Applications using high voltage VCOs (P/P + 1). IF/RF local oscillator (LO) generation in base stations Point-to-point radio LO generation A simple 3-wire interface controls all of the on-chip registers. Clock for analog-to-digital and digital-to-analog converters The devices operate with a power supply ranging from 2.7 V to Wireless LANs, PMR 5.5 V and can be powered down when not in use. Communications test equipment FUNCTIONAL BLOCK DIAGRAM AV DV V R SET DD DD P CPGND REFERENCE 14-BIT REF IN R COUNTER PHASE CHARGE CP FREQUENCY PUMP DETECTOR 14 R COUNTER LATCH CURRENT LOCK SETTING DETECT CLK 24-BIT FUNCTION DATA INPUT REGISTER LATCH 22 LE A, B COUNTER SD OUT HIGH Z LATCH FROM 19 AV FUNCTION DD MUX LATCH MUXOUT 13 N = BP + A SD 13-BIT OUT B COUNTER LOAD RF A IN PRESCALER P/P + 1 M3 M2 M1 RF B IN LOAD 6-BIT A COUNTER ADF4113HV 6 CE AGND DGND Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. rights of third parties that may result from its use. Specifications subject to change without notice. No Tel: 781.329.4700 20072012 Analog Devices, Inc. All rights reserved. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com 06223-001ADF4113HV Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Prescaler (P/P + 1) ........................................................................9 Applications ....................................................................................... 1 A and B Counters ..........................................................................9 Functional Block Diagram .............................................................. 1 R Counter .......................................................................................9 Revision History ............................................................................... 2 Phase Frequency Detector (PFD) and Charge Pump ............ 10 Specifications ..................................................................................... 3 Muxout and Lock Detect ........................................................... 10 Timing Characteristics ................................................................ 4 Input Shift Register .................................................................... 10 Absolute Maximum Ratings ............................................................ 5 Function Latch ............................................................................ 13 Transistor Count ........................................................................... 5 Applications ..................................................................................... 15 Thermal Resistance ...................................................................... 5 Using a Digitial-to-Analog Converter to Drive the R Pin .................................................................................. 15 SET ESD Caution .................................................................................. 5 Interfacing ................................................................................... 15 Pin Configurations and Function Descriptions ........................... 6 PCB Design Guidelines for Chip Scale Package .................... 16 Typical Performance Characteristics ............................................. 7 Outline Dimensions ....................................................................... 17 Circuit Description ........................................................................... 9 Ordering Guide .......................................................................... 17 Reference Input Section ............................................................... 9 RF Input Stage ............................................................................... 9 REVISION HISTORY 10/12Rev. A to Rev. B Changed CP-20-1 Package to CP-20-6 Package ............. Universal Changes to Table 3 and Table 4 ....................................................... 5 Added EPAD Notation..................................................................... 6 Updated Outline Dimensions ....................................................... 17 Changes to Ordering Guide .......................................................... 17 9/08Rev. 0 to Rev. A Changes to Figure 22 ...................................................................... 13 1/07Revision 0: Initial Version Rev. B Page 2 of 20

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